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JUNE 2003
XRT75L03D
REV. 1.0.0
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
TRANSMITTER:
GENERAL DESCRIPTION
The XRT75L03D is a three-channel fully integrated Line Interface Unit (LIU) with Jitter Attenuator for E3/ DS3/STS-1 applications. It incorporates 3 independent Receivers, Transmitters and Jitter Attenuators in a single 128 pin LQFP package. Each channel of the XRT75L03D can be independently configured to operate in the data rate, E3 (34.368 MHz), DS3 (44.736 MHz) or STS-1 (51.84 MHz). Each transmitter can be turned off and tristated for redundancy support or for conserving power. The XRT75L03D's differential receiver provides high noise interference margin and is able to receive the data over 1000 feet of cable or with up to 12 dB of cable attenuation. The XRT75L03D incorporates an advanced crystalless jitter attenuator per channel that can be selected either in the transmit or receive path. The jitter attenuator performance meets the ETSI TBR-24 and Bellcore GR-499 specifications. The XRT75L03D provides both Serial Microprocessor Interface as well as Hardware mode for programming and control. The XRT75L03D supports local, remote and digital loop-backs. The device also has a built-in Pseudo Random Binary Sequence (PRBS) generator and detector with the ability to insert and detect single bit error for diagnostic purposes.
* Compliant with Bellcore GR-499, GR-253 and ANSI
T1.102 Specification for transmit pulse
* Tri-state Transmit output capability for redundancy
applications
* Each Transmitter can be turned on or off * Transmitters provide Current Drive Output
JITTER ATTENUATOR:
* On chip advanced crystal-less Jitter Attenuator for
each channel
* Jitter Attenuator can be selected in Receive or
Transmit paths
* Meets ETSI TBR 24 Jitter Transfer Requirements * Compliant with jitter transfer template outlined in
ITU G.751, G.752, G.755 and GR-499-CORE,1995 standards
* Jitter Attenuator can be disabled
CONTROL AND DIAGNOSTICS:
* 5 wire Serial Microprocessor Interface for control
and configuration
* Supports
monitoring
optional
internal
Transmit
driver
* Hardware Mode for control and configuration * Each channel supports Local, Remote and Digital
Loop-backs
FEATURES
RECEIVER:
* On chip Clock and Data Recovery circuit for high
input jitter tolerance
* Single 3.3 V 5% power supply * 5 V Tolerant I/O * Available in 128 pin Thermally enhanced LQFP
Package
* Meets E3/DS3/STS-1 Jitter Tolerance Requirement * Detects and Clears LOS as per G.775 * Receiver Monitor mode handles up to 20 dB flat
loss with 6 dB cable attenuation
* - 40C to 85C Industrial Temperature Range APPLICATIONS * E3/DS3 Access Equipment * STS1-SPE to DS3 De-Synchronizing * DSLAMs * Digital Cross Connect Systems * CSU/DSU Equipment * Routers * Fiber Optic Terminals
* On chip B3ZS/HDB3 encoder and decoder that can
be either enabled or disabled
* On-chip clock synthesizer provides the appropriate
rate clock from a single 12.288 MHz Clock
* Provides low jitter output clock
Exar Corporation 48720 Kato Road, Fremont CA, 94538 * (510) 668-7000 * FAX (510) 668-7017 * www.exar.com
XRT75L03D THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.0 FIGURE 1. BLOCK DIAGRAM OF THE XRT 75L03D
SD I SD O IN T SC lk CS R E SE T
ac
X R T 75L 03 D
Serial Processor Interface
CLKOU T E3 C lk,D S3 C lk, ST S -1C lk R L O L _(n ) R xO N R xC lkIN V
H O ST /H W ST S -1/D S3 _(n ) E3 _(n ) R EQ EN _(n ) R T IP_(n ) R R in g _(n ) SR /D R L L B _(n ) L O ST H R T T IP _(n ) T R in g_ (n ) M T IP _(n) M R in g_ (n ) D M O _(n )
Peak Detector
Clock S ynthesizer
Invert HDB 3/ B3ZS Decoder
R xC lk_ (n ) R P O S _(n ) R N E G _ (n)/ L C V_ (n )
AG C/ Equalizer
Slicer
Clock & Data Rec overy
Jitter Attenuator
M UX
Local LoopBack
LO S Detector
Rem ote LoopB ack
R L B _(n ) R L O S_(n ) JA T x/R x
Line Driver
Tx Pulse Shaping
Tim ing Control
Jitter A ttenuator
M UX
HDB 3/ B3ZS Encoder
T PD a ta_ (n) T N D ata_ (n ) T xC lk_ (n ) T AO S _(n )
D evice Monitor
Tx Control
C h an n el 0 C h an n el 1 C h an n el 2
T xL E V_ (n ) T xO N _(n )
N o te s: 1. (n ) = 0, 1 o r 2 fo r resp ec tive C h an n els 2. S eria l Pro ce s so r In terface in p u t p in s a re sh a re d b y th e th ree C h an n els in "H o s t" M o d e an d red efin ed in th e "H a rd w a re" M o d e.
TRANSMIT INTERFACE CHARACTERISTICS
* Accepts either Single-Rail or Dual-Rail data from Terminal Equipment and generates a bipolar signal to the
line
* Integrated Pulse Shaping Circuit * Built-in B3ZS/HDB3 Encoder (which can be disabled) * Accepts Transmit Clock with duty cycle of 30%-70% * Generates pulses that comply with the ITU-T G.703 pulse template for E3 applications * Generates pulses that comply with the DSX-3 pulse template, as specified in Bellcore GR-499-CORE and
ANSI T1.102_1993
* Generates pulses that comply with the STSX-1 pulse template, as specified in Bellcore GR-253-CORE * Transmitter can be turned off in order to support redundancy designs
RECEIVE INTERFACE CHARACTERISTICS
* Integrated Adaptive Receive Equalization (optional) for optimal Clock and Data Recovery * Declares and Clears the LOS defect per ITU-T G.775 requirements for E3 and DS3 applications * Meets Jitter Tolerance Requirements, as specified in ITU-T G.823_1993 for E3 Applications * Meets Jitter Tolerance Requirements, as specified in Bellcore GR-499-CORE for DS3 Applications * Declares Loss of Signal (LOS) and Loss of Lock (LOL) Alarms * Built-in B3ZS/HDB3 Decoder (which can be disabled) * Recovered Data can be muted while the LOS Condition is declared * Outputs either Single-Rail or Dual-Rail data to the Terminal Equipment
2
ac
R LO L_1 R LO S _1 EXDGND SFM _E N E 3 C lk /C L K _ E N D S 3 C lk /C L K _ O U T S T S -1 C lk /1 2 M EXDVDD R xD V D D _ 1 RPOS_1 R N E G _ 1 /L C V _ 1 R xC lk _ 1 R xD G N D _ 1 AG N D _1 JAD G N D JAG N D _1 JAD V DD JAV D D_1 REFAV DD R XA R XB REFG ND T xO N _ 2 T xA G N D _ 1 DM O_1 T xA V D D _ 1
PART NUMBER
103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
FIGURE 2. PIN OUT OF THE XRT75L03D
XRT75L03DIV
X R T75L03D
PACKAGE
ORDERING INFORMATION
XRT75L03D THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.0
128 Pin LQFP
3
OPERATING TEMPERATURE RANGE - 40C to + 85C
TxO N _1 T N D a ta _ 1 T P D a ta _ 1 T x C lk _ 1 M R in g _ 1 M T IP _ 1 TAO S _1 TAO S _2 TxLEV_1 TxLEV_2 T T IP _ 1 TxV DD _1 T R in g _ 1 TxG N D _1 TxA G ND _2 M R in g _ 2 M T IP _ 2 TxG N D _2 T R in g _ 2 TxV DD _2 T T IP _ 2 DMO_2 TxA VD D_2 T N D a ta _ 2 T P D a ta _ 2 T x C lk _ 2 TxG N D _0 T R in g _ 0 TxV DD _0 T T IP _ 0 M T IP _ 0 M R in g _ 0 T N D a ta _ 0 T P D a ta _ 0 T x C lk _ 0 TxLEV_0 TAO S _0 TxO N _0 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 R LO L_2 R LO S _2 IC T R LO L_0 R LO S _0 R xD G ND _0 RPOS_0 R N E G _ 0 /L C V _ 0 R x C lk _ 0 R xD VD D _0 R xD VD D _2 RPOS_2 R N E G _ 2 /L C V _ 2 R x C lk _ 2 R xD G ND _2 AG N D _0 JAG N D _2 JAG N D _0 JAV D D_0 JAV D D_2 JA0 J A T x /R x JA1 TxA G ND _0 DMO_0 TxA VD D_0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
TES T RESET AG N D _2 LO STHR S T S -1 /D S 3 _ 1 LLB _1 R LB _1 REQEN_1 E3_1 R xAV DD _1 R R in g _ 1 R T IP _ 1 R xAG N D _1 R xAG N D _2 R T IP _ 2 R R in g _ 2 R xAV DD _2 E3_2 REQEN_2 R LB _2 LLB _2 S T S -1 /D S 3 _ 2 R xAG N D _0 R T IP _ 0 R R in g _ 0 R xAV DD _0 E3_0 REQEN_0 R LB _0 LLB _0 S T S -1 /D S 3 _ 0 L O S M U T /IN T H O S T /H W R x M O N /S D O R x O N /S D I T x C lk IN V /S C lk R x C lk IN V /C S S R /D R
XRT75L03D THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.0 FEATURES .................................................................................................................................................... APPLICATIONS .............................................................................................................................................. TRANSMIT INTERFACE CHARACTERISTICS ...................................................................................................... RECEIVE INTERFACE CHARACTERISTICS ........................................................................................................ Figure 1. Block Diagram of the XRT 75L03D .................................................................................................... Figure 2. Pin Out of the XRT75L03D ................................................................................................................ ORDERING INFORMATION ................................................................................................................... 3
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1 1 2 2 2 3
GENERAL DESCRIPTION ............................................................................................... 1
PIN DESCRIPTIONS (BY FUNCTION) ............................................................................. 4
SYSTEM-SIDE TRANSMIT INPUT AND TRANSMIT CONTROL PINS ...................................................................... 4 TRANSMIT LINE SIDE PINS ............................................................................................................................ 8 SYSTEM-SIDE RECEIVE OUTPUT AND RECEIVE CONTROL PINS .................................................................... 10 RECEIVE LINE SIDE PINS ............................................................................................................................ 17 CLOCK INTERFACE ...................................................................................................................................... 18 GENERAL CONTROL PINS ........................................................................................................................... 19 CONTROL AND ALARM INTERFACE ............................................................................................................... 21 JITTER ATTENUATOR INTERFACE ................................................................................................................. 21 POWER SUPPLY AND GROUND PINS ............................................................................................................ 24 XRT75L03D PIN LISTING IN NUMERICAL ORDER ......................................................................................... 26 1.0 ELECTRICAL CHARACTERISTICS ................................................................................................. 31 TABLE 1: ABSOLUTE MAXIMUM RATINGS ............................................................................................................ 31 TABLE 2: DC ELECTRICAL CHARACTERISTICS: ................................................................................................... 31 2.0 TIMING CHARACTERISTICS ............................................................................................................ 32 Figure 3. Typical interface between terminal equipment and the XRT75L03D (dual-rail data) ....................... 32 Figure 4. Transmitter Terminal Input Timing ................................................................................................... 32 Figure 5. Receiver Data output and code violation timing .............................................................................. 33 Figure 6. Transmit Pulse Amplitude test circuit for E3, DS3 and STS-1 Rates ............................................... 33 3.0 LINE SIDE CHARACTERISTICS: ..................................................................................................... 34
3.1 E3 LINE SIDE PARAMETERS: ............................................................................................................................. 34
Figure 7. Pulse Mask for E3 (34.368 mbits/s) interface as per itu-t G.703 ..................................................... TABLE 3: E3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS ........................... Figure 8. Bellcore GR-253 CORE Transmit Output Pulse Template for SONET STS-1 Applications ............ TABLE 4: STS-1 PULSE MASK EQUATIONS ........................................................................................................ TABLE 5: STS-1 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS (GR-253) . Figure 9. Transmit Ouput Pulse Template for DS3 as per Bellcore GR-499 .................................................. TABLE 6: DS3 PULSE MASK EQUATIONS ........................................................................................................... TABLE 7: DS3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS (GR-499) ..... Figure 10. Microprocessor Serial Interface Structure ...................................................................................... Figure 11. Timing Diagram for the Microprocessor Serial Interface ................................................................ TABLE 8: MICROPROCESSOR SERIAL INTERFACE TIMINGS ( TA = 250C, VDD=3.3V 5% AND LOAD = 10PF) .....
34 35 36 36 37 38 38 39 39 40 40
FUNCTIONAL DESCRIPTION: ........................................................................................ 41
4.0 The Transmitter Section: ................................................................................................................. 41 Figure 12. Single-Rail or NRZ Data Format (Encoder and Decoder are Enabled) ......................................... 41 Figure 13. Dual-Rail Data Format (encoder and decoder are disabled) ......................................................... 41
4.1 TRANSMIT CLOCK: ........................................................................................................................................... 4.2 B3ZS/HDB3 ENCODER: .................................................................................................................................. 4.2.1 B3ZS Encoding: ................................................................................................................................. 4.2.2 HDB3 Encoding: ................................................................................................................................. 42 42 42 42
Figure 14. B3ZS Encoding Format ................................................................................................................. 42 Figure 15. HDB3 Encoding Format ................................................................................................................. 42
4.3 TRANSMIT PULSE SHAPER: .............................................................................................................................. 43 4.3.1 Guidelines for using Transmit Build Out Circuit: ............................................................................ 43 4.3.2 Interfacing to the line: ........................................................................................................................ 43 4.4 TRANSMIT DRIVE MONITOR: ............................................................................................................................. 44 4.5 TRANSMITTER SECTION ON/OFF: ...................................................................................................................... 44
5.0 The Receiver Section: ...................................................................................................................... 44
I
XRT75L03D THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.0
5.1 AGC/EQUALIZER: ............................................................................................................................................ 44
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Figure 16. Transmit Driver Monitor set-up. ..................................................................................................... 44
5.1.1 Interference Tolerance: ..................................................................................................................... 45
Figure 17. Interference Margin Test Set up for DS3/STS-1 ........................................................................... 45
5.2 CLOCK AND DATA RECOVERY: ......................................................................................................................... 46
Figure 18. Interference Margin Test Set up for E3. ........................................................................................ 46 TABLE 9: INTERFERENCE MARGIN TEST RESULTS .............................................................................................. 46
5.3 B3ZS/HDB3 DECODER: .................................................................................................................................. 47 5.4 LOS (LOSS OF SIGNAL) DETECTOR: ................................................................................................................ 47 5.4.1 DS3/STS-1 LOS Condition: ................................................................................................................ 47
DISABLING ALOS/DLOS DETECTION: ......................................................................................................... 47
5.4.2 E3 LOS Condition: ............................................................................................................................. 47
TABLE 10: THE ALOS (ANALOG LOS) DECLARATION AND CLEARANCE THRESHOLDS FOR A GIVEN SETTING OF LOSTHR AND REQEN (DS3 AND STS-1 APPLICATIONS) ................................................................... 47 Figure 19. Loss Of Signal Definition for E3 as per ITU-T G.775 .................................................................... 48 Figure 20. Loss of Signal Definition for E3 as per ITU-T G.775. .................................................................... 48
5.4.3 Muting the Recovered Data with LOS condition: ............................................................................ 49
6.0 Jitter: ................................................................................................................................................. 49
6.1 JITTER TOLERANCE - RECEIVER: ...................................................................................................................... 49 6.1.1 DS3/STS-1 Jitter Tolerance Requirements: ..................................................................................... 49
Figure 21. Jitter Tolerance Measurements ..................................................................................................... 49
6.1.2 E3 Jitter Tolerance Requirements: ................................................................................................... 50
Figure 22. Input Jitter Tolerance For DS3/STS-1 .......................................................................................... 50 Figure 23. Input Jitter Tolerance for E3 ......................................................................................................... 50
6.2 JITTER TRANSFER - RECEIVER/TRANSMITTER: .................................................................................................. 51 6.3 JITTER ATTENUATOR: ...................................................................................................................................... 51
TABLE 11: JITTER AMPLITUDE VERSUS MODULATION FREQUENCY (JITTER TOLERANCE) ..................................... 51 TABLE 12: JITTER TRANSFER SPECIFICATION/REFERENCES ............................................................................... 51
6.3.1 Jitter Generation: ............................................................................................................................... 52
7.0 Serial Host interface: ....................................................................................................................... 52 TABLE 13: JITTER TRANSFER PASS MASKS ....................................................................................................... 52 Figure 24. Jitter Transfer Requirements and Jitter Attenuator Performance .................................................. 52 TABLE 14: FUNCTIONS OF SHARED PINS ............................................................................................................ 53 TABLE 15: XRT75L03D REGISTER MAP - QUICK LOOK ..................................................................................... 54 ................................................................................................................................................................. 56 THE REGISTER MAP AND DESCRIPTION FOR THE XRT75L03D 3-CHANNEL DS3/E3/STS-1 LIU IC .. 56
Legend: ..................................................................................................................................................................56
TABLE 16: COMMAND REGISTER ADDRESS MAP, WITHIN THE XRT75L03D 3-CHANNEL DS3/E3/STS-1 LIU W/ JITTER ATTENUATOR IC ................................................................................................................................. 56 THE GLOBAL/CHIP-LEVEL REGISTERS ............................................................................................... 58 ................................................................................................................................................................. 58 REGISTER DESCRIPTION - GLOBAL REGISTERS .............................................................................. 58 TABLE 17: LIST AND ADDRESS LOCATIONS OF GLOBAL REGISTERS .................................................................... 58 TABLE 18: APS/REDUNDANCY CONTROL REGISTER - CR0 (ADDRESS LOCATION = 0X00) .................................. 58 TABLE 19: BLOCK LEVEL INTERRUPT ENABLE REGISTER - CR32 (ADDRESS LOCATION = 0X20) ......................... 61 TABLE 20: BLOCK LEVEL INTERRUPT STATUS REGISTER - CR33 (ADDRESS LOCATION = 0X21) ......................... 62 TABLE 21: DEVICE/PART NUMBER REGISTER - CR62 (ADDRESS LOCATION = 0X3E) .......................................... 63 ................................................................................................................................................................. 64 THE PER-CHANNEL REGISTERS ......................................................................................................... 64 TABLE 22: CHIP REVISION NUMBER REGISTER - CR63 (ADDRESS LOCATION = 0X3F) ........................................ 64 TABLE 23: COMMAND REGISTER ADDRESS MAP, WITHIN THE XRT75L03D 3-CHANNEL DS3/E3/STS-1 LIU W/ JITTER ATTENUATOR IC ................................................................................................................................. 64 REGISTER DESCRIPTION - PER CHANNEL REGISTERS ................................................................... 66 TABLE 24: SOURCE LEVEL INTERRUPT ENABLE REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X01 ................. 66 TABLE 25: SOURCE LEVEL INTERRUPT STATUS REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X02 ................. 68
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XRT75L03D THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.0 TABLE 26: ALARM STATUS REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X03 ................................................ TABLE 27: TRANSMIT CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X04 ......................................... TABLE 28: RECEIVE CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X05 ........................................... TABLE 29: CHANNEL CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X06 ......................................... TABLE 30: JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07 ......................... 8.0 Diagnostic Features: ........................................................................................................................
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70 75 78 80 83 85
8.1 PRBS GENERATOR AND DETECTOR: ................................................................................................................ 85 8.2 LOOPBACKS: ............................................................................................................................................... 85 8.2.1 ANALOG LOOPBACK: ....................................................................................................................... 85
Figure 25. PRBS MODE ................................................................................................................................. 85 Figure 26. Analog Loopback ........................................................................................................................... 86
8.2.2 DIGITAL LOOPBACK: ........................................................................................................................ 87 8.2.3 REMOTE LOOPBACK: ....................................................................................................................... 87
Figure 27. Digital Loopback ............................................................................................................................ 87 Figure 28. Remote Loopback .......................................................................................................................... 87
8.3 TRANSMIT ALL ONES (TAOS): ................................................................................................................... 88
Figure 29. Transmit All Ones (TAOS) ............................................................................................................. 88 9.0 THE SONET/SDH DE-SYNC FUNCTION WITHIN THE XRT75L03D ............................................... 89
9.1 BACKGROUND AND DETAILED INFORMATION - SONET DE-SYNC APPLICATIONS .......................... 89
Figure 30. A Simple Illustration of a DS3 signal being mapped into and transported over the SONET Network 90
9.2 MAPPING/DE-MAPPING JITTER/WANDER ................................................................................................ 91 9.2.1 HOW DS3 DATA IS MAPPED INTO SONET ...................................................................................... 91
Figure 31. A Simple Illustration of the SONET STS-1 Frame ......................................................................... 92 Figure 32. A Simple Illustration of the STS-1 Frame Structure with the TOH and the Envelope Capacity Bytes Designated .................................................................................................................................... 93 Figure 33. The Byte-Format of the TOH within an STS-1 Frame .................................................................... 94 Figure 34. The Byte-Format of the TOH within an STS-1 Frame .................................................................... 95 Figure 35. Illustration of the Byte Structure of the STS-1 SPE ....................................................................... 96 Figure 36. An Illustration of Telcordia GR-253-CORE's Recommendation on how map DS3 data into an STS-1 SPE ............................................................................................................................................... 97 Figure 37. A Simplified "Bit-Oriented" Version of Telcordia GR-253-CORE's Recommendation on how to map DS3 data into an STS-1 SPE ........................................................................................................ 97
9.2.2 DS3 Frequency Offsets and the Use of the "Stuff Opportunity" Bits ............................................ 98
Figure 38. A Simple Illustration of a DS3 Data-Stream being Mapped into an STS-1 SPE, via a PTE .......... 99 Figure 39. An Illustration of the STS-1 SPE traffic that will be generated by the "Source" PTE, when mapping in a DS3 signal that has a bit rate of 44.736Mbps + 1ppm, into an STS-1 signal .......................... 100
9.3 JITTER/WANDER DUE TO POINTER ADJUSTMENTS .......................................................................................... 102 9.3.1 The Concept of an STS-1 SPE Pointer ........................................................................................... 102
Figure 40. An Illustration of the STS-1 SPE traffic that will be generated by the Source PTE, when mapping a DS3 signal that has a bit rate of 44.736Mbps - 1ppm, into an STS-1 signal .............................. 102 Figure 41. An Illustration of an STS-1 SPE straddling across two consecutive STS-1 frames ..................... 103
9.3.2 Pointer Adjustments within the SONET Network .......................................................................... 104
Figure 42. The Bit-format of the 16-Bit Word (consisting of the H1 and H2 bytes) with the 10 bits, reflecting the location of the J1 byte, designated ............................................................................................. 104 Figure 43. The Relationship between the Contents of the "Pointer Bits" (e.g., the 10-bit expression within the H1 and H2 bytes) and the Location of the J1 Byte within the Envelope Capacity of an STS-1 Frame ... 104
9.3.3 Causes of Pointer Adjustments ...................................................................................................... 105
Figure 44. An Illustration of an STS-1 signal being processed via a Slip Buffer ........................................... 106 Figure 45. An Illustration of the Bit Format within the 16-bit word (consisting of the H1 and H2 bytes) with the "I" bits designated ............................................................................................................................ 107 Figure 46. An Illustration of the Bit-Format within the 16-bit word (consisting of the H1 and H2 bytes) with the "D" bits designated ...................................................................................................................... 108
9.3.4 Why are we talking about Pointer Adjustments? .......................................................................... 109 9.4 CLOCK GAPPING JITTER ................................................................................................................................. 109
Figure 47. Illustration of the Typical Applications for the XRT75L03D in a SONET De-Sync Application .... 109
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XRT75L03D THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.0
PLICATIONS
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9.5 A REVIEW OF THE CATEGORY I INTRINSIC JITTER REQUIREMENTS (PER TELCORDIA GR-253-CORE) FOR DS3 AP........................................................................................................................................................................ 110
TABLE 31: SUMMARY OF "CATEGORY I INTRINSIC JITTER REQUIREMENT PER TELCORDIA GR-253-CORE, FOR DS3 APPLICATIONS .................................................................................................................................. 110
9.5.1 DS3 De-Mapping Jitter ..................................................................................................................... 111 9.5.2 Single Pointer Adjustment .............................................................................................................. 111
Figure 48. Illustration of Single Pointer Adjustment Scenario ...................................................................... 111
9.5.3 Pointer Burst .................................................................................................................................... 112 9.5.4 Phase Transients ............................................................................................................................. 112
Figure 49. Illustration of Burst of Pointer Adjustment Scenario .................................................................... 112 Figure 50. Illustration of "Phase-Transient" Pointer Adjustment Scenario ................................................... 112
9.5.5 87-3 Pattern ...................................................................................................................................... 113 9.5.6 87-3 Add ............................................................................................................................................ 113
Figure 51. An Illustration of the 87-3 Continuous Pointer Adjustment Pattern ............................................. 113
9.5.7 87-3 Cancel ....................................................................................................................................... 114
Figure 52. Illustration of the 87-3 Add Pointer Adjustment Pattern .............................................................. 114 Figure 53. Illustration of 87-3 Cancel Pointer Adjustment Scenario ............................................................. 114
9.5.8 Continuous Pattern .......................................................................................................................... 115 9.5.9 Continuous Add .............................................................................................................................. 115
Figure 54. Illustration of Continuous Periodic Pointer Adjustment Scenario ............................................... 115
9.5.10 Continuous Cancel ........................................................................................................................ 116
Figure 55. Illustration of Continuous-Add Pointer Adjustment Scenario ....................................................... 116 Figure 56. Illustration of Continuous-Cancel Pointer Adjustment Scenario .................................................. 116
9.6 A REVIEW OF THE DS3 WANDER REQUIREMENTS PER ANSI T1.105.03B-1997. ............................................. 117 9.7 A REVIEW OF THE INTRINSIC JITTER AND WANDER CAPABILITIES OF THE XRT75L03D IN A TYPICAL SYSTEM APPLICATION ............................................................................................................................................................................ 117 9.7.1 Intrinsic Jitter Test results .............................................................................................................. 117
TABLE 32: SUMMARY OF "CATEGORY I INTRINSIC JITTER TEST RESULTS" FOR SONET/DS3 APPLICATIONS ..... 117
9.7.2 Wander Measurement Test Results ............................................................................................... 118 9.8 DESIGNING WITH THE XRT75L03D ................................................................................................................. 118 9.8.1 How to design and configure the XRT75L03D to permit a system to meet the above-mentioned Intrinsic Jitter and Wander requirements ..................................................................................................................... 118
Figure 57. Illustration of the XRT75L03D being connected to a Mapper IC for SONET De-Sync Applications .. 118 CHANNEL CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X06 ................................................. 119 CHANNEL 1 ADDRESS LOCATION = 0X0E ......................................... 119 CHANNEL 2 ADDRESS LOCATION = 0X16 ......................................... 119 CHANNEL CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X06 ................................................. 120 CHANNEL 1 ADDRESS LOCATION = 0X0E .............................................. 120 CHANNEL 2 ADDRESS LOCATION = 0X16 ............................................... 120 JITTER ATTENUATOR CONTROL REGISTER - (CHANNEL 0 ADDRESS LOCATION = 0X07 ............................... 120 CHANNEL 1 ADDRESS LOCATION = 0X0F .................................. 120 CHANNEL 2 ADDRESS LOCATION = 0X17 .................................. 120
9.8.2 Recommendations on Pre-Processing the Gapped Clocks (from the Mapper/ASIC Device) prior to routing this DS3 Clock and Data-Signals to the Transmit Inputs of the XRT75L03D .............................................. 121
JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07 ................................ CHANNEL 1 ADDRESS LOCATION = 0X0F ............................ CHANNEL 2 ADDRESS LOCATION = 0X17 ............................ JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07 ................................ CHANNEL 1 ADDRESS LOCATION = 0X0F ........................... CHANNEL 2 ADDRESS LOCATION = 0X17 ........................... Figure 58. Illustration of MINOR PATTERN P1 ............................................................................................ Figure 59. Illustration of MINOR PATTERN P2 ............................................................................................ Figure 60. Illustration of Procedure which is used to Synthesize MAJOR PATTERN A .............................. Figure 61. Illustration of MINOR PATTERN P3 ............................................................................................ Figure 62. Illustration of Procedure which is used to Synthesize PATTERN B ........................................... Figure 63. Illustration of the SUPER PATTERN which is output via the "OC-N to DS3" Mapper IC ............
121 121 121 121 121 121 122 123 123 124 124 125
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XRT75L03D THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.0
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Figure 64. Simple Illustration of the XRT75L03D being used in a SONET De-Synchronizer" Application ... 125
9.8.3 How does the XRT75L03D permit the user to comply with the SONET APS Recovery Time requirements of 50ms (per Telcordia GR-253-CORE)? ........................................................................................................... 126
TABLE 33: MEASURED APS RECOVERY TIME AS A FUNCTION OF DS3 PPM OFFSET .......................................... 126
9.8.4 How should one configure the XRT75L03D, if one needs to support "Daisy-Chain" Testing at the end Customer's site? ..................................................................................................................................................... 127
JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07 ................................. 127 CHANNEL 1 ADDRESS LOCATION = 0X0F ............................ 127 CHANNEL 2 ADDRESS LOCATION = 0X17 ............................ 127 JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07 ................................. 127 CHANNEL 1 ADDRESS LOCATION = 0X0F ................................... 127 CHANNEL 2 ADDRESS LOCATION = 0X17 ................................... 127 ORDERING INFORMATION ............................................................................................................... 128 PACKAGE DIMENSIONS - 14X20 MM, 128 PIN PACKAGE .............................................................................. 128 REVISIONS ............................................................................................................................................... 129
V
XRT75L03D THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.0
ac
PIN DESCRIPTIONS (BY FUNCTION)
SYSTEM-SIDE TRANSMIT INPUT AND TRANSMIT CONTROL PINS
PIN # 38 1 125 SIGNAL NAME TxON_0 TxON_1 TxON_2 TYPE I DESCRIPTION
Transmitter ON Input - Channel 0: Transmitter ON Input - Channel 1: Transmitter ON Input - Channel 2:
These input pins are used to either enable or disable the Transmit Output Driver corresponding to Channel_n. "Low" - Disables the Transmit Output Driver of the corresponding Channel. In this setting, the corresponding TTIP_n and TRING_n output pins will be tri-stated. "High" - Enables the Transmit Output Driver of the corresponding Channel. In this setting, the corresponding TTIP_n and TRING_n output pins will be enabled.
NOTES: 1. Even when the XRT75L03D is configured in HOST mode, these pins will be active. To enable software control of the Transmit Output Driver outputs, pull these pins "High". 2. When Transmitters are turned off either in Host or Hardware mode, the TTIP and TRing outputs are Tri-stated. 3. These pins are internally pulled "High"
35 4 26 TxClk_0 TxClk_1 TxClk_2 I
Transmit Clock Input - Channel 0: Transmit Clock Input f - Channel 1: Transmit Clock Input - Channel 2:
These input pins have two functions:
* They function as the timing source for the Transmit Section of the
corresponding channel within the XRT75L03D.
* They also are used by the Transmit Section of the LIU IC to sample the
corresponding TPDATA_n and TNDATA_n input pin.
NOTE: The user is expected to supply a 44.736MHz 20ppm clock signal (for DS3 applications), 34.368MHz 20 ppm clock signal (for E3 applications) or a 51.84MHz 4.6ppm clock signal (for STS-1, Stratum 3E or better applications).
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XRT75L03D THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.0 SYSTEM-SIDE TRANSMIT INPUT AND TRANSMIT CONTROL PINS
PIN # 34 3 25 SIGNAL NAME TPDATA_0/TxDATA_0 TPDATA_1/TxDATA_1 TPDATA_2/TxDATA_2 TYPE I DESCRIPTION
ac
Transmit Positive Data Input - Channel 0: Transmit Positive Data Input - Channel 1: Transmit Positive Data Input - Channel 2:
Transmit Positive Data/Data Input - Channel n: The function of these input pins depends upon whether the corresponding channel has been configured to operate in the Single-Rail or Dual-Rail Mode. Single Rail Mode - Transmit Data Input - Channel n: If the Channel has been configured to operate in the Single-Rail Mode, then all transmit output data will be serially applied to this input pin. This signal will latched into the Transmit Section circuitry upon either the rising or falling edge of the TxCLK_n signal, depending upon user configuration. In the Single-Rail Mode, the Transmit Section of the LIU IC will then encode this data into either the B3ZS line code (for DS3 and STS-1 applications) or the HDB3 line code (for E3 applications). Dual Rail Mode - Transmit Positive Data Input - Channel n: If the Channel has been configured to operate in the Dual-Rail Mode, then the user should apply a pulse to this input pin, anytime the Transmit Section of the LIU IC is suppose to generate and transmit a positive-polarity pulse onto the line. This signal will be latched into the Transmit Section circuitry upon either the rising or falling edge of the TxCLK_n signal, depending upon user configuration. In the Dual-Rail Mode, the Transmit Section of the LIU IC will NOT encode this data into either the B3ZS or HDB3 line codes. If the user configures the LIU IC to operate in the Dual-Rail Mode, then B3ZS/HDB3 encoding must have already been done prior to providing the transmit output data to this input pin.
33 2 24
TNData_0 TNData_1 TNData_2
I
Transmit Negative Data Input - Channel 0: Transmit Negative Data Input - Channel 1: Transmit Negative Data Input - Channel 2:
If a Channel has been configured to operate in the Dual-Rail Mode, then the user should apply a pulse to this input pin anytime the Transmit Section of the LIU IC is suppose to generate and transmit a negative-polarity pulse onto the line. This signal will be latched into the Transmit Section circuitry upon either the rising or falling edge of the TxCLK_n signal, depending upon user configuration.
NOTE: If the Channel has been configured operate in the Single-Rail Mode, then this input pin has no function, and should be tied to GND.
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XRT75L03D THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.0 SYSTEM-SIDE TRANSMIT INPUT AND TRANSMIT CONTROL PINS
PIN # 37 7 8 SIGNAL NAME TAOS_0 TAOS_1 TAOS_2 TYPE I DESCRIPTION
ac
Transmit "All Ones" Input - Channel 0: Transmit "All Ones" Input - Channel 1: Transmit "All Ones" Input - Channel 2:
These input pin are used to configure the Transmit Section of the corresponding channel to generate and transmit an unframed "All Ones" pattern via the DS3, E3 or STS-1 line signal to the remote terminal equipment. When this configuration is implemented the Transmit Section will ignore the data that it is accepting from the System-side equipment and will overwrite this data will the "All Ones" Pattern. "Low" - Does not configure the channel to transmit an unframed "All Ones" Pattern to the remote terminal equipment. In this mode, the Transmit Section of the Channel will output data based upon the signals that are applied to the TxPOS_n and TxNEG_n input pins. "High" - Configures the Channel to transmit an unframed "All Ones" Pattern to the remote terminal equipment. In this mode, the Transmit Section will override the data that is applied to the TxPOS_n and TxNEG_n input pins, and will proceed to generate and transmit an unframed "All Ones" pattern.
4. This input pin is ignored if the XRT75L03D is operating in the HOST Mode and should be tied to GND. 5. These input pins are internally pulled down.
36 9 10 TxLEV_0 TxLEV_1 TxLEV_2 I Transmit Line Build-Out Enable/Disable Select - Channel 0: Transmit Line Build-Out Enable/Disable Select - Channel 1: Transmit Line Build-Out Enable/Disable Select - Channel 2: These input pins are used to enable or disable the Transmit Line Build-Out (e.g., pulse-shaping) circuit within the corresponding channel. The user should set these input pins either "High" or "Low" based upon the following guidelines. "Low" - If the cable length between the Transmit Output of the corresponding Channel and the DSX-3/STSX-1 location is 225 feet or less. "High" - If the cable length between the Transmit Output of the corresponding Channel and the DSX-3/STSX-1 location is 225 feet or more.
NOTES: 1. These guidelines must be followed in order to insure that the Transmit Section of Channel_n will always generate a DS3 pulse that complies with the Isolated Pulse Template requirements per Bellcore GR-499-CORE, or an STS-1 pulse that complies with the Pulse Template requirements per Telcordia GR-253-CORE. 2. This input pin is inactive if the XRT75L03D has been configured to operate in the Host Mode, or if the corresponding channel has been configured to operate in the E3 Mode. If either of these cases are true, then tie this input pin to GND. 3. These input pins are internally pulled "Low".
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XRT75L03D THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.0 SYSTEM-SIDE TRANSMIT INPUT AND TRANSMIT CONTROL PINS
PIN # 40 127 22 SIGNAL NAME DMO_0 DMO_1 DMO_2 TYPE O DESCRIPTION
ac
Drive Monitor Output - Channel 0: Drive Monitor Output - Channel 1: Drive Monitor Output - Channel 2:
These output signals are used to indicate some sort of fault condition within the Transmit Output signal path. This output pin will toggle "High" anytime the Transmit Drive Monitor circuitry either, via the corresponding MTIP and MRING input pins or internally, detects no bipolar pulses via the Transmit Output line signal (e.g., via the TTIP_n and TRING_n output pins) for 128 bit-periods. This output pin will be driven "Low" anytime the Transmit Drive Monitor circuitry has detected at least one bipolar pulse via the Transmit Output line signal within the last 128 bit periods.
67
TxClkINV/ SClk
I
Hardware Mode: Transmit Clock Invert Host Mode: Serial Clock Input: Hardware mode This input pin is used to select the edge of the TxCLK_n input that the Transmit Section of all channels will use to sample the TPDATA_n and TNDATA_n input pins. Setting this input pin "High" configures all three Transmitters to sample the TPData_n and TNData_n data on the rising edge of the TxClk_n . Setting this input pin "Low" configures all three Transmitters to sample the TPData_n and TNData_n data on the falling edge of the TxClk_n . Host Mode In the Host Mode this pin functions as SClk input pin please refer to the pin descriptions for the Microprocessor interface.
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XRT75L03D THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.0 TRANSMIT LINE SIDE PINS
PIN # 30 11 21 SIGNAL NAME TTIP_0 TTIP_1 TTIP_2 TYPE O DESCRIPTION
ac
Transmit TTIP Output - Positive Polarity Signal - Channel 0: Transmit TTIP Output - Positive Polarity Signal - Channel 1: Transmit TTIP Output - Positive Polarity Signal - Channel 2:
These output pins along with the corresponding TRING_n output pins, function as the Transmit DS3/E3/STS-1 Line output signal drivers for a given channel, of the XRT75L03D. Connect this signal and the corresponding TRING_n output signal to a 1:1 transformer. Whenever the Transmit Section of the Channel generates and transmits a positive-polarity pulse onto the line, this output pin will be pulsed to a "higher-voltage" than its corresponding TRING_n output pins. Conversely, whenever the Transmit Section of the Channel generates and transmit a negative-polarity pulse onto the line, this output pin will be pulsed to a "lower-voltage" than its corresponding TRING_n output pin.
NOTE: This output pin will be tri-stated whenever the corresponding TxON_n input pin or bit-field is set to "0".
28 13 19 TRing_0 TRing_1 TRing_2 O
Transmit Ring Output - Negative Polarity Signal - Channel 0: Transmit Ring Output - Negative Polarity Signal - Channel 1: Transmit Ring Output - Negative Polarity Signal - Channel 2:
These output pins along with the corresponding TTIP_n output pins, function as the Transmit DS3/E3/STS-1 Line output signal drivers for a given channel, within the XRT75L03D. Connect this signal and the corresponding TTIP_n output signal to a 1:1 transformer. Whenever the Transmit Section of the Channel generates and transmits a positive-polarity pulse onto the line. This output pin will be pulsed to a "lower-voltage" than its corresponding TTIP_n output pins. Conversely, whenever the Transmit Section of the Channel generates and transmit a negative-polarity pulse onto the line. This output pin will be pulsed to a "higher-voltage" than its corresponding TTIP_n output pin.
NOTE: This output pin will be tri-stated whenever the corresponding TxON_n input pin or bit-field is set to "0".
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XRT75L03D THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.0 TRANSMIT LINE SIDE PINS
PIN # 31 6 17 SIGNAL NAME MTIP_0 MTIP_1 MTIP_2 TYPE I DESCRIPTION
ac
Monitor Tip Input - Positive Polarity Signal - Channel 0: Monitor Tip Input - Positive Polarity Signal - Channel 1: Monitor Tip Input - Positive Polarity Signal - Channel 2:
These input pins along with MRING_n function as the Transmit Drive Monitor Output (DMO) input monitoring pins. To (1) monitor the Transmit Output line signal and (2) to perform this monitoring externally, then this pin MUST be connected to the corresponding TTIP_n output pin via a 274 ohm series resistor. Similarly, the MRING_n input pin MUST also be connected to its corresponding TRING_n output pin via a 274 ohm series resistor. The MTIP_n and MRING_n input pins will continuously monitor the Transmit Output line signal via the TTIP_n and TRING_n output pins for bipolar activity. If these pins do not detect any bipolar activity for 128 bit periods, then the Transmit Drive Monitor circuit will drive the corresponding DMO_n output pin "High" in order to denote a possible fault condition in the Transmit Output Line signal path.
NOTES: 1. These input pins are inactive if the user choose to internally monitor the Transmit Output line signal. 2. Internal Monitoring is only available as an option if the XRT75L03D in is being operated in the Host Mode.
32 5 16 MRing_0 MRing_1 MRing_2 I
Monitor Ring Input - Channel 0: Monitor Ring Input - Channel 1: Monitor Ring Input - Channel 2:
These input pins along with MTIP_n function as the Transmit Drive Monitor Output (DMO) input monitoring pins. To (1) monitor the Transmit Output line signal and (2) to perform this monitoring externally, then this input pin MUST be connected to the corresponding TRING_n output pin via a 274 ohm series resistor. Similarly, the MTIP_n input pin MUST be connected to its corresponding TTIP_n output pin via a 274 ohm series resistor. The MTIP_n and MRING_n input pins will continuously monitor the Transmit Output line signal via the TTIP_n and TRING_n output pins for bipolar activity. If these pins do not detect any bipolar activity for 128 bit periods, then the Transmit Drive Monitor circuit will drive the corresponding DMO_n output pin "High" to indicate a possible fault condition in the Transmit Output Line signal path.
NOTES: 1. These input pins are inactive if the user chooses to internally monitor the Transmit Output line signal. 2. Internal Monitoring is only available as an option if the XRT75L03D is being operated in the Host Mode.
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XRT75L03D THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.0 SYSTEM-SIDE RECEIVE OUTPUT AND RECEIVE CONTROL PINS
PIN # 60 104 63 SIGNAL NAME RLOS_0 RLOS_1 RLOS_2 TYPE O DESCRIPTION
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Receive Loss of Signal Output Indicator - Channel 0: Receive Loss of Signal Output Indicator - Channel 1: Receive Loss of Signal Output Indicator - Channel 2:
This output pin indicates whether or not the corresponding channel is declaring the Loss of Signal (LOS) Defect condition. "Low" - Indicates that the corresponding Channel is NOT currently declaring the LOS defect condition. "High" - Indicates that the corresponding Channel is currently declaring the LOS defect condition.
61 103 64
RLOL_0 RLOL_1 RLOL_2
O
Receive Loss of Lock Output Indicator - Channel 0: Receive Loss of Lock Output Indicator - Channel 1: Receive Loss of Lock Output Indicator - Channel 2:
This output pin indicates whether or not the corresponding channel is declaring the Loss of Lock (LOL) Condition. "Low" - Indicates that the corresponding Channel is NOT declaring the LOL condition. "High" - Indicates that the corresponding Channel is currently declaring the LOL condition.
NOTE: The Receive Section of a given channel will declare the LOL condition anytime the frequency of the Recovered Clock (RCLK) signal differs from that of the E3CLK input clock signal (if the channel is operating in the E3 Mode), the DS3CLK input clock signal (if the channel is operating in the DS3 Mode) the STS-1CLK input clock signal (if the channel is operating in the STS-1 Mode), or that clock signal which is derived from the SFM Clock Synthesizer block (if the chip is operating in the Single-Frequency Mode) by 0.5% (or 5000ppm) or more.
58 112 53 RPOS_0/RDATA_0 RPOS_1/RDATA_1 RPOS_2/RDATA_2 O
Receive Positive Data Output - Receive Data Output - Channel 0: Receive Positive Data Output - Receive Data Output - Channel 1: Receive Positive Data Output - Receive Data Output - Channel 2:
The function of these output pins depends upon whether the channel/device has been configured to operate in the Single-Rail or Dual-Rail Mode. Dual-Rail Mode - Receive Positive Polarity Data Output If the channel/device has been configured to operate in the Dual-Rail Mode, then all positive-polarity data will be output via this output pin. The negativepolarity data will be output via the corresponding RNEG_n output pin. In other words, the Receive Section of the corresponding Channel will pulse this output pin "High" for one period of RCLK_n anytime it receives a positive-polarity pulse via the RTIP/RRING input pins. The data that is output via this pin is updated upon a user-selectable edge of the RCLK_n output clock signal. Single-Rail Mode - Receive Data Output If the channel/device has been configured to operate in the Single-Rail Mode, then all Receive (or Recovered) data will be output via this output pin. The data that is output via this pin is updated upon a user-selectable edge of the RCLK_n output clock signal.
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XRT75L03D THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.0 SYSTEM-SIDE RECEIVE OUTPUT AND RECEIVE CONTROL PINS
PIN # 57 113 52 SIGNAL NAME RNEG_0/LCV_0 RNEG_1/LCV_1 RNEG_2/LCV_2 TYPE O DESCRIPTION
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Receive Negative Data Output/Line Code Violation Indicator Channel 0: Receive Negative Data Output/Line Code Violation Indicator Channel 1: Receive Negative Data Output/Line Code Violation Indicator Channel 2:
The function of these pins depends on whether the XRT75L03D is configured in Single Rail or Dual Rail mode. Dual-Rail Mode - Receive Negative Polarity Data Output If the channel/device has been configured to operate in the Dual-Rail Mode, then all negative-polarity data will be output via this output pin. The positivepolarity data will be output via the corresponding RPOS_n output pin. In other words, the Receive Section of the corresponding Channel will pulse this output pin "High" for one period of RCLK_n anytime it receives a negative-polarity pulse via the RTIP/RRING input pins. The data that is output via this pin is updated upon a user-selectable edge of the RCLK_n output clock signal. Single-Rail Mode - Line Code Violation Indicator Output If the channel/device has been configured to operate in the Single-Rail Mode, then this particular output pin will function as the Line Code Violation indicator output. In this configuration, the Receive Section of the Channel will pulse this output pin "High" for at least one RCLK period whenever it detects either an LCV (Line Code Violation) or an EXZ (Excessive Zero Event). The data that is output via this pin is updated upon a user-selectable edge of the RCLK_n output clock signal.
56 114 51
RxClk_0 RxClk_1 RxClk_2
O
Receive Clock Output - Channel 0: Receive Clock Output - Channel 1: Receive Clock Output - Channel 2: This output pin functions as the Receive or recovered clock signal. All Receive (or recovered) data will output via the RPOS_n and RNEG_n outputs upon the user-selectable edge of this clock signal. Additionally, if the device/channel has been configured to operate in the SingleRail Mode, then the RNEG_n/LCV_n output pins will also be updated upon the user-selectable edge of this clock signal.
75 95 84
REQEN_0 REQEN_1 REQEN_2
I
Receive Equalization Enable Input - Channel 0: Receive Equalization Enable Input - Channel 1: Receive Equalization Enable Input - Channel 2: These input pins are used to either enable or disable the Receive Equalizer block within the Receive Section of the corresponding channel. "Low" - Disables the Receive Equalizer within the corresponding channel. "High" - Enables the Receive Equalizer within the corresponding channel.
NOTES: 1. For virtually all applications, it is recommend that this input pin be pulled "High" and enable the Receive Equalizer. 2. This input pin ignored and should be tied to GND if the XRT75L03D has been configured to operate in the Host Mode. 3. These input pins are internally pulled low.
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XRT75L03D THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.0 SYSTEM-SIDE RECEIVE OUTPUT AND RECEIVE CONTROL PINS
PIN # 71 SIGNAL NAME LOSMUT/ INT TYPE I/O DESCRIPTION Muting Upon LOS Enable/Interrupt Output Pin This input pin is used to configure the Receive Section, in each of the three channels within the chip, to automatically pull their corresponding Recovered Data Output pins (e.g. RPOS_n and RNEG_n) to GND anytime and for the duration that the Receive Section declares the LOS defect condition. In other words, this feature if enabled will cause the Receive Channel to automatically mute the Recovered data anytime and for the duration that the Receive Section declares the LOS defect condition. "Low" - Disables the Muting upon LOS feature. In this setting the Receive Section will NOT automatically mute the Recovered Data whenever it is declaring the LOS defect condition. "High" - Enables the Muting upon LOS feature. In this setting the Receive Section will automatically mute the Recovered Data whenever it is declaring the LOS defect condition.
ac
NOTES: 1. This input pin is will function as the Interrupt Request output pin within the Microprocessor Serial Interface, if the XRT75L03D has been configured to operate in the Host Mode. 2. This configuration setting applies globally to each of the three (3) channels within the XRT75L03D.
99 LOSTHR I Analog LOS Detector Threshold Level Select Input: This input pin permits the user to select both of the following parameters for the Analog LOS Detector within each of the three Receive Sections within the XRT75L03D. 1. The Analog LOS Defect Declaration Threshold (e.g., the maximum signal level that the Receive Section of a given channel must detect before declaring the LOS Defect condition), and 2. The Analog LOS Defect Clearance Threshold (e.g., the minimum signal level that the Receive Section of a given channel must detect before clearing the LOS Defect condition) Setting this input pin "High" selects one set of Analog LOS Defect Declaration and Clearance thresholds. Setting this input pin "Low" selects the other set of Analog LOS Defect Declaration and Clearance thresholds. Please see Table 10 for more details.
NOTE: This input pin is only active if at least one channel within the XRT75L03D has been configured to operate in the DS3 or STS-1 Modes.
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XRT75L03D THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.0 SYSTEM-SIDE RECEIVE OUTPUT AND RECEIVE CONTROL PINS
PIN # 69 SIGNAL NAME RxMON/ SDO TYPE I DESCRIPTION Receiver Monitor Mode Enable:
ac
This input pin permits the user to configure each of the three (3) Receive Sections within the XRT75L03D, into the Receiver Monitor Mode. If the user configures each of the Receive Sections into the Receive Monitor Mode, then each of the Receiver Sections will be able to receive a nominal DSX-3/STSX-1 signal that has been attenuated by 20dB of flat loss along with 6dB of cable loss, in an error-free manner, and without declaring the LOS defect condition. "Low" - Configures each of the Receive Sections to operate in the Normal Mode. "High" - Configures each of the Receive Sections to operate in the Receive Monitor Mode.
NOTES: 1. This input pin will function as the SDO (Serial Data Output pin within the Microprocessor Serial Interface) whenever the XRT75L03D has been configured to operate in the Host Mode. 2. This configuration setting applies globally to all three (3) of the channels within the XRT75L03D.
68 RxON/ SDI I Receive ON: This input pin permits the user to either turn on or turn off each of the three (3) Receive Sections within the XRT75L03D. If the user turns on the Receive Sections of each channel, then all three channels will begin to receive the incoming DS3, E3 or STS-1 data-streams via the RTIP_n and RRING_n input pins. Conversely, if the user turns off the Receive Section, then the entire Receive Section (e.g., the AGC and Receive Equalizer blocks, Clock Recovery PLL, etc.) will be powered down. "Low" - Shuts off the Receive Sections within each of the three (3) Channels in the XRT75L03D. "High" - Turns on the Receive Sections within each of the three (3) Channels in the XRT75L03D.
NOTES: 1. This input pin will function as the SDI (Serial Data Input pin within the Microprocessor Serial Interface) whenever the XRT75L03D has been configured to operate in the Host Mode. 2. This configuration setting applies globally to all three (3) of the channels within the XRT75L03D. 3. This pin is internally pulled low.
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XRT75L03D THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.0 SYSTEM-SIDE RECEIVE OUTPUT AND RECEIVE CONTROL PINS
PIN # 66 SIGNAL NAME RxClkINV/ CS TYPE I DESCRIPTION Receive Clock Invert Input - Chip Selectl: In Hardware Mode is pin is used to configure the Receive Sections of the three (3) channels in the XRT75L03D to either output the recovered data via the RPOS_n or RNEG_n/LCV_n output pins upon either the rising or falling edge of the RCLK_n clock output signal. "Low" - Configures each of the Receive Sections to output the recovered data via the RPOS_n and RNEG_n/LCV_n output pins upon the rising edge of the RCLK_n output clock signal. "High" - Configures each of the Receive Sections to output the recovered data via the RPOS_n and RNEG_n/LCV_n output pins upon the falling edge of the RCLK_n output clock signal.
ac
NOTES: 1. This input pin will function as the CS (Chip Select Input pin) of the Microprocessor Serial Interface when the XRT75L03D has been configured to operate in the Host Mode. 2. This configuration setting applies globally to all three (3) of the channels within the XRT75L03D. 3. If the Receive Sections are configured to operate in the Single-Rail Mode, then the LCV_n output pin will be updated on the user-selected edge of the RCLK_n signal, per this configuration selection.
106 SFM_EN I Single Frequency Mode Enable: This input pin is used to configure the XRT75L03D to operate in the SFM (Single Frequency) Mode. When this feature is invoked the Single-Frequency Mode Synthesizer will become active. By applying a 12.288MHz clock signal to pin 109, STS-1CLK/ 12M the XRT75L03D will, depending upon which mode the user has configured each of the three channels, generate all of the appropriate clock signals (e.g., 34.368MHz, 44.736MHz or 51.84. Further, the XRT75L03D internal circuitry will route each of these synthesized clock signals to the appropriate nodes of the corresponding three channels in the XRT75L03D. "Low" - Disables the Single Frequency Mode. In this configuration setting, the user is required to supply to the E3CLK, DS3CLK or STS-1CLK input pins all of the relevant clock signals that are to be used within the chip. "High" - Enables the Single-Frequency Mode. A 12.288MHz clock signal MUST be applied to pin 109 (STS-1CLK/12M).
NOTE: This input pin is internally pulled low.
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XRT75L03D THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.0 SYSTEM-SIDE RECEIVE OUTPUT AND RECEIVE CONTROL PINS
PIN # 107 SIGNAL NAME E3Clk/ CLK_EN TYPE I DESCRIPTION E3 Reference Clock Input/SFM Clock Output Enable:
ac
The function of this chip depends upon whether or not the XRT75L03D has been configured to operate in the Single-Frequency Mode. If NOT operating in the Single-Frequency Mode If the XRT75L03D has NOT been configured to operate in the SFM (Single Frequency) Mode, and if at least one channel is to be operated in the E3 Mode, then a 34.368MHz clock signal must be applied to this input pin. If the user does not intend to operate the device in the SFM Mode nor operate any of the channels in the E3 Mode tie this input signal to GND. If operating in the Single-Frequency Mode If the XRT75L03D is operated in the SFM Mode and is to output a clock signal that is synthesized from the SFM Clock Synthesizer PLL so that the user's system can use this clock signal as a timing source, pull this input pin to a logic "High". If the user pull this input pin "High", then the XRT75L03D will output the line rate clock signal that has been synthesized for Channel 1, via pin 108 (DS3CLK/ CLK_OUT). For example, if Channel 1 is configured to operate in the STS-1 Mode and this input pin is pulled "High", then the XRT75L03D will output a 51.84MHz clock signal via the CLK_OUT pin.
15
XRT75L03D THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.0 SYSTEM-SIDE RECEIVE OUTPUT AND RECEIVE CONTROL PINS
PIN # 108 SIGNAL NAME DS3Clk/ CLK_OUT TYPE I/O DESCRIPTION DS3 Reference Clock Input/SFM Synthesizer Clock Output: The function of this chip depends upon whether or not the XRT75L03D has been configured to operate in the SFM Mode. If NOT operating in the Single-Frequency Mode If the XRT75L03D has NOT been configured to operate in the SFM Mode, and if at least one channel of the XRT75L03D is configured in the DS3 Mode, then a clock signal with a frequency of 44.736 MHz 20ppm must be applied to this input pin. If the XRT75L03D is not configured to operate in the SFM Mode and none of the channels are to be operated in the DS3 Mode, tie this input signal to GND. If operating in the Single-Frequency Mode If the XRT75L03D is configured to operate in the SFM Mode, and if pin 107 (E3CLK/CLKEN) is pulled to a logic "High", then the SFM Clock Synthesizer PLL generated line rate clock signal for Channel 1 will be output via this output pin. In this mode, this particular output pin can be used by the user's system as a timing source. 109 STS-1Clk/ 12M I STS-1 Reference Clock Input/12.288MHz SFM Reference Clock Input: The function of this pin depends upon whether or not the XRT75L03D has been configured to operate in the SFM Mode. If NOT operating in the Single-Frequency Mode If the XRT75L03D has NOT been configured to operate in the SFM Mode and if at least one channel is intended to operate in the STS-1 Mode, then the user must supply a clock signal with a frequency of 51.84MHz 4.6ppm to this input pin If the XRT75L03D is not to be operatedin the SFM Mode and none of the channels are to be operated in the STS-1 Mode, tie this input signal to GND. If operating in the Single-Frequency Mode If the user has configured the XRT75L03D has been configured to operate in the SFM Mode a clock signal with a frequency of 12.288MHz 20ppm MUST be applied to this input pin. The SFM Synthesizer will then synthesize one of the appropriate line rate frequencies (e.g., 34.368MHz for E3, 44.736MHz for DS3, and 51.84MHz for STS-1) based upon this 12.288MHz Reference Clock source.
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16
XRT75L03D THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.0 RECEIVE LINE SIDE PINS
PIN # 79 91 88 SIGNAL NAME RTIP_0 RTIP_1 RTIP_2 TYPE I DESCRIPTION
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Receive TIP Input - Channel 0: Receive TIP Input - Channel 1: Receive TIP Input - Channel 2:
These input pins along with the corresponding RRing_n input pin function as the Receive DS3/E3/STS-1 Line input signal receiver for a given channel of the XRT75L03D. Cconnect this signal and the corresponding RRING_n input signal to a 1:1 transformer. Whenever the RTIP/RRING input pins are receiving a positive-polarity pulse within the incoming DS3, E3 or STS-1 line signal, then this input pin will be pulsed to a "higher-voltage" than its corresponding RRING_n input pin. Conversely, whenever the RTIP/RRING input pins are receiving a negativepolarity pulse within the incoming DS3, E3 or STS-1 line signal, then this input pin will be pulsed to a "lower-voltage" than its corresponding RRING_n input pin.
78 92 87
RRing_0 RRing_1 RRing_2
I
Receive Ring Input - Channel 0: Receive Ring Input - Channel 1: Receive Ring Input - Channel 2:
These input pins along with the corresponding RTIP_n input pin function as the Receive DS3/E3/STS-1 Line input signal receiver for a given channel of the XRT75L03D. Connect this signal and the corresponding RTIP_n input signal to a 1:1 transformer. Whenever the RTIP/RRING input pins are receiving a positive-polarity pulse within the incoming DS3, E3 or STS-1 line signal, then this input pin will be pulsed to a "lower-voltage" than its corresponding RTIP_n input pin. Conversely, whenever the RTIP/RRING input pins are receiving a negativepolarity pulse within the incoming DS3, E3 or STS-1 line signal, then this input pin will be pulsed to a "higher-voltage" than its corresponding RTIP_n input pin.
17
XRT75L03D THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.0 CLOCK INTERFACE
PIN # 107 SIGNAL NAME E3Clk/ CLK_EN TYPE I DESCRIPTION E3 Clock Input (34.368 MHz 20 ppm): If all the 3 channels or any one of the channels is configured in E3 mode, a reference clock 34.368 MHz 20 ppm is input to this pin.. Clock Output Enable: If the Single Frequency Mode is selected, tie this pin "High" to enable the clock output through the CLK_OUT pin (pin 108). 108 DS3Clk/ CLK_OUT I/O DS3 Clock Input (44.736 MHz 20 ppm): If all the 3 channels or any one of the channels is configured in DS3 mode, a reference clock 44.736 MHz 20 ppm is input to this pin. Clock Output: When the Single Frequency Mode is enabled, this pin is configured as the clock output from Channel 1.This clock frequency is determined by the Channel 1 setting..
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NOTE: This low jitter output clock can be used as the input clock source for the framer device. thus eliminating the need for a separate clock source for the framer.
109 STS-1Clk/ 12M I STS-1 Clock Input (51.84 MHz 20 ppm): If all the 3 channels or any one of the channels is configured in STS-1 mode, a reference clock 51.84 MHz 20 ppm is input to this pin. Single Frequency Mode Clock Input: In Single Frequency Mode, a reference clock of 12.288 MHz 20 ppm is connected to this pin and the internal clock synthesizer generates the appropriate clock frequencies based on the configuration of the rates (E3 or DS3 or STS-1).
18
XRT75L03D THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.0 GENERAL CONTROL PINS
PIN # 65 SIGNAL NAME SR/DR TYPE I DESCRIPTION Single-Rail/Dual-Rail Select Input - Chip Level This input pin is used to configure the XRT75L03D to operate in either the Single-Rail or Dual-Rail Mode. If the XRT75L03D is configured to operate in the Single-Rail Mode, then all of the following will happen.
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* All of the B3ZS/HDB3 Encoder and Decoder blocks in the XRT75L03D will be
enabled.
* The Transmit Section of each channel will accept all of the outbound data
from the System-side Equipment via the TPDATA_n (or TxDATA_n) input pin.
* The Receive Section of each channel will output all of the recovered data to
the System-side Equipment via the RPOS output pin.
* Each of the RNEG/LCV output pins will now function as the LCV (Line Code
Violation or Excessive Zero Event) indicator output pin. If the user configures the device to operate in the Dual-Rail Mode, then all of the following will happen.
* All of the B3ZS/HDB3 Encoder and Decoder blocks in the XRT75L03D will be
disabled.*
* The Transmit Section of each channel will accept positive-polarity data via the
TPDATA_n input pin, and negative-polarity data via the TNDATA_n input pin.
* The Receive Section of each channel will pulse the RPOS_n output pin "High"
for one period of RCLK_n for each time a positive-polarity pulse is received via the RTIP_n/RRING_n input pins
* Likewise, the Receive Section of each channel will also pulse the RNEG_n
output pin "High" for one period of RCLK_n for each time a negative-polarity pulse is received via the RTIP_n/RRING_n input pins. "Low" - Configures the XRT75L03D to operate in the Dual-Rail Mode. "High" - Configures the XRT75L03D to operate in the Single-Rail Mode.
NOTES: 1. This input pin is ignored and should be tied to GND if the XRT75L03D has been configured to operate in the Host Mode. 2. This pin is internally pulled "Low".
76 94 85 E3_0 E3_1 E3_2 I E3 Mode Select Input - Channel 0 E3 Mode Select Input - Channel1 E3 Mode Select Input - Channel 2 This input pin, along with the corresponding STS-1/DS3_n input pin is used the to configure a given channel within the XRT75L03D into either the DS3, E3 or STS-1 Modes. "High" - Configures the corresponding channel to operate in the E3 Mode. "Low" - Configures the corresponding channel to operate in either the DS3 or STS-1 Modes, depending upon the setting of the corresponding STS-1/DS3_n input pin.
NOTES: 1. This input pin is ignored and should be tied to GND if the XRT75L03D has been configured to operate in the Host Mode. 2. This input pin is internally pulled low.
19
XRT75L03D THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.0 GENERAL CONTROL PINS
PIN # 72 98 81 SIGNAL NAME STS-1/DS3_0 STS-1/DS3_1 STS-1/DS3_2 TYPE I DESCRIPTION STS-1/DS3 Select Input - Channel 0 STS-1/DS3 Select Input - Channel 1 STS-1/DS3 Select Input - Channel 2 This input pin, along with the corresponding E3_n input pin is used the to configure a given channel within the XRT75L03D into either the DS3, E3 or STS-1 Modes. "High" - Configures the corresponding channel to operate in the STS-1 Mode provided that the corresponding E3_n input pin is pulled "Low". "Low" - Configures the corresponding channel to operate in DS3 Mode provided that the corresponding E3_n input pin is pulled "Low".
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NOTES: 1. This input pin is ignored and should be tied to GND if the XRT75L03D has been configured to operate in the Host Mode or if the corresponding E3_n input pin is pulled "High". 2. This input pin is internally pulled low.
74 96 83 RLB_0 RLB_1 RLB_2 I
Remote Loop-back - RLB Input - Channel 0: Remote Loop-back - RLB Input - Channel 1: Remote Loop-back - RLB Input - Channel 2:
This input pin along with LLB_n is used to configure different Loop-Back modes.
RLB_n 0 0 1 1
LLB_n 0 1 0 1
Loopback Mode Normal (No Loop-Back) Mode Analog Loop-Back Mode Remote Loop-Back Mode Digital Local Loop-Back Mode
NOTE:
73 97 82 LLB_0 LLB_1 LLB_2 I
This input pin is ignored and should be connected to GND if the XRT75L03D is operating in the HOST Mode.
Loop-Back Select - LLB Input - Channel 0 Loop-Back Select - LLB Input - Channel 1 Loop-Back Select - LLB Input - Channel 2 Please see description above for RLB_n
102
TEST
****
Factory Test Mode Input Pin This pin must be connected to GND for normal operation.
NOTE: This input pin is internally pulled "Low".
20
XRT75L03D THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.0 GENERAL CONTROL PINS
PIN # 62 SIGNAL NAME ICT TYPE I DESCRIPTION
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In-Circuit Test Input:
Setting this pin "Low" causes all digital and analog outputs to go into a highimpedance state to allow for in-circuit testing. For normal operation, set this pin "High".
NOTE: This pin is internally pulled "High".
70 HOST/HW I HOST/Hardware Mode Select: Tie this pin "High" to configure the XRT75L03D in HOST mode. Tie this "Low" to configure in Hardware mode. When the XRT75L03D is configured in HOST mode, the states of many of the discrete input pins are controlled by internal register bits.
NOTE: This pin is internally pulled up.
CONTROL AND ALARM INTERFACE
PIN # 122 SIGNAL NAME RXA TYPE **** DESCRIPTION External Resistor of 3.01K 1%. Should be connected between RxA and RxB for internal bias. 123 RXB **** External Resistor of 3.01K 1%. Should be connected between RxA and RxB for internal bias.
JITTER ATTENUATOR INTERFACE
PIN # 44 SIGNAL NAME JA0 TYPE I Jitter Attenuator Select 0: In Hardware Mode, this pin along with pin 42 configures the Jitter Attenuator as shown in the table below. DESCRIPTION
JA0 0 0 1 1
NOTES:
JA1 0 1 0 1
Mode FIFO Depth = 16 bits FIFO Depth = 32 bits SONET/SDH De-Sync Mode Jitter Attenuator Disabled
1. The setting of these input pins applies globally to all three (3) channels in the XRT75L03D. 2. This input pin is ignored and should be tied to GND if the XRT75L03D is configured to operate in the Host Mode.
21
XRT75L03D THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.0 JITTER ATTENUATOR INTERFACE
42 JA1 I Jitter Attenuator Select 1: Please see the Description above for JA0 43 JATx/Rx I Jitter Attenuator in Transmit/Receive Path Select Input: This input pin is used to configure the Jitter Attenuator to operate in either the Transmit or Receive path within each of the three (3) channels of the XRT75L03D. "Low" - Configures the Jitter Attenuator within each channel to operate in the Receive Path. "High" - Configures the Jitter Attenuator within each channel to operate in the Transmit Path.
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NOTES: 1. The setting of this input pin applies globally to all three (3) channels of the XRT75L03D. 2. This input pin is ignored and should be tied to GND if the XRT75L03D is configured to operate in the Host Mode or if the Jitter Attenuators are disabled.
MICROPROCESSOR SERIAL INTERFACE - (HOST MODE)
PIN # 69 SIGNAL NAME SDO/RxMON TYPE I/O DESCRIPTION Microprocessor Serial Interface - Serial Data Output: This pin serially outputs the contents of a specified on-chip Command Register during READ Operations via the Microprocessor Serial Interface. The data which is output via this pin is updated upon the falling edge of the SCLK clock signal. This output pin will be tri-stated upon completion of a given READ operation.
NOTE: This pin functions as the RxMON input pin if the XRT75L03D has been configured to operate in the Hardware Mode.
68 SDI/RxON I Microprocessor Serial Interface - Serial Data Input: This input pin functions as the Serial Data Input pin for the Microprocessor Serial Interface. In particular, this input pin will accept all of the following data in a serial manner during READ and WRITE operations with the Microprocessor Serial Interface.
* The READ/WRITE indicator bit. * The Address Value of the Targeted Command Register for this particular
READ or WRITE operation.
* The Data to be written into the targeted Command Register for a given
WRITE operation. All data that is applied to this input will be sampled upon the rising edge of the SCLK input clock signal.
NOTE: This input pin will function as the RxON input pin if the XRT75L03D has been configured to operate in the Hardware Mode.
22
XRT75L03D THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.0 MICROPROCESSOR SERIAL INTERFACE - (HOST MODE)
PIN # 67 SIGNAL NAME SClk/TCLKINV TYPE I DESCRIPTION Microprocessor Serial Interface -Serial Clock Input: This input pin functions as the Clock Source for the Microprocessor Serial Interface. Each time the user wishes to perform a READ or WRITE operate with the onchip Command Registers via the Microprocessor Serial Interface, the user MUST do the following.
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* Assert the CS input pin by toggling it "Low", and * Provide 16 Clock Periods to this particular input pin for each READ and
WRITE operation. The Microprocessor Serial Interface will sample any data residing upon the SDI input pin, upon the rising edge of this clock signal. Further, for READ operations, the Microprocessor Serial Interface will serially output the contents of a target Command Register upon the falling edge of this clock signal.
NOTE: The maximum frequency of this particular clock signal is 10MHz.
66 CS/RCLKINV I Microprocessor Serial Interface - Chip Select Input: This input pin should be pulled "Low" whenever a READ or WRITE operation is to be executed to the on-chip Command Registers, via the Microprocessor Serial Interface. This input pin should remain "Low" until the READ or WRITE operation has been completed. This input pin should be pulled "High" at all other times.
NOTE: If the XRT75L03D has been configured to operate in the Host Mode then this input pin will function as the RCLKINV input pin.
71 INT/LOSMUT O Microprocessor Serial Interface - Interrupt Request Output: If the XRT75L03D has been configured to operate in the Host Mode, then this pin becomes the Interrupt Request Output for the XRT75L03D. During normal conditions, this output pin will be pulled "High". However, if the user enables certain interrupts within the device, and if those conditions occur, then the XRT75L03D will request an interrupt from the Microprocessor by toggling this output pin "Low".
NOTES: 1. If the XRT75L03D is configured to operate in the Hardware Mode, then this pin functions as the LOSMUT input pin. 2. This pin will remain "Low" until the Interrupt has been served.
101 RESET I Microprocessor Serial Interface - H/W RESET Input: Pulsing this input "Low" causes the XRT75L03D to reset the contents of the onchip Command Registers to their default values. As a consequence, the XRT75L03D will then also be operating in its default condition. For normal operation pull this input pin to a logic "High".
NOTE: This input pin is internally pulled high.
23
XRT75L03D THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.0 POWER SUPPLY AND GROUND PINS
PIN # PIN NAME TYPE RECEIVE ANALOG VDD 77 93 86 RxAVDD_0 RxAVDD_1 RxAVDD_2 TRANSMIT ANALOG VDD 39 128 23 121 TxAVDD_0 TxAVDD_1 TxAVDD_2 REFAVDD JITTER ATTENUATOR ANALOG VDD 46 120 45 JAVDD_0 JAVDD_1 JAVDD_2 DIGITAL VDD 29 12 20 55 111 54 119 110 TxVDD_0 TxVDD_1 TxVDD_2 RxDVDD_0 RxDVDD_1 RxDVDD_2 JADVDD EXDVDD **** **** **** **** DESCRIPTION
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24
XRT75L03D THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.0 POWER SUPPLY AND GROUND PINS
PIN # PIN NAME TYPE GROUNDS 41 126 15 80 90 89 47 118 48 49 116 100 124 27 14 18 59 115 50 117 105 TxAGND_0 TxAGND_1 TxAGND_2 RxAGND_0 RxAGND_1 RxAGND_2 JAGND_0 JAGND_1 JAGND_2 AGND_0 AGND_1 AGND_2 REFGND TxGND_0 TxGND_1 TxGND_2 RxDGND_0 RxDGND_1 RxDGND_2 JADGND EXDGND **** DESCRIPTION
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25
XRT75L03D THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.0
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XRT75L03D PIN LISTING IN NUMERICAL ORDER
PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 PIN NAME TxON_1 TNDATA_1 TPDATA_1 TCLK_1 MRING_1 MTIP_1 TAOS_1 TAOS_2 TxLEV_1 TxLEV_2 TTIP_1 DVDD TRING_1 TxAGND_1 TxAGND_2 MRING_2 MTIP_2 GND TRING_2 TxVDD_2 TTIP_2 DMO_2 TxAVDD_2 TNDATA_2 TPDATA_2 TCLK_2 TxGND_0 TRING_0 TxVDD_0 TTIP_0 TYPE I I I I I I I I I I O *** O *** *** I I *** O *** O O *** I I I *** O *** O 1. Not Active while in Host Mode 2. This input pin is internally pulled low. 1. Not Active while in Host Mode 2. This input pin is internally pulled low. 1. Not Active while in Host Mode 2. This input pin is internally pulled low. 1. Not Active while in Host Mode 2. This input pin is internally pulled low. COMMENTS This input pin is internally pulled 'High'.
26
XRT75L03D THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.0 XRT75L03D PIN LISTING IN NUMERICAL ORDER
PIN # 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 PIN NAME MTIP_0 MRING_0 TNDATA_0 TPDATA_0 TAOS_0 TxLEV_0 TAOS_0 TxON_0 TxAVDD_0 DMO_0 TxAGND_0 JA1 JATx/Rx JA0 JAVDD_2 JAVDD_0 JAGND_0 JAGND_2 AGND_0 RxDGND_2 RCLK_2 RNEG_2/LCV_2 RPOS_2 RxDVDD_2 RxDVDD_0 RCLK_0 RNEG_0/LCV_0 RPOS_0 RxDGND_0 RLOS_0 RLOL_0 ICT TYPE I I I I I I I I *** O *** I I I *** *** *** *** *** *** O O O *** *** O O O *** O O I This input pin is internally pulled low. Not Active while in Host Mode Not Active while in Host Mode Not Active while in Host Mode Not Active while in Host Mode 1. Not Active while in Host Mode 2. This input pin is internally pulled low. 1. Not Active while in Host Mode 2. This input pin is internally pulled low. This input pin is internally pulled 'High'. COMMENTS
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27
XRT75L03D THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.0 XRT75L03D PIN LISTING IN NUMERICAL ORDER
PIN # 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 PIN NAME RLOS_2 RLOL_2 SR/DR RCLKINV (CS) TCLKINV (SCLK) RxON (SDI) RxMON (SDO) HOST/HW LOSMUT (INT) STS-1/DS3_0 LLB_0 RLB_0 REQEN_0 E3_0 RxAVDD_0 RRING_0 RTIP_0 RxAGND_0 STS-1/DS3_2 LLB_2 RLB_2 REQEN_2 E3_2 RxAVDD_2 RRING_2 RTIP_2 RxAGND_2 RxAGND_1 RTIP_1 TYPE O O I I I I I/O I I/O I I I I I *** I I *** I I I I I *** I I *** *** I 1. Not Active while in Host Mode 2. This input pin is internally pulled low. Not Active while in Host Mode Not Active while in Host Mode 1. Not Active while in Host Mode 2. This input pin is internally pulled low. 1. Not Active while in Host Mode 2. This input pin is internally pulled low. 1. Not Active while in Host Mode 2. This input pin is internally pulled low. Not Active while in Host Mode Not Active while in Host Mode 1. Not Active while in Host Mode 2. This input pin is internally pulled low. 1. Not Active while in Host Mode 2. This input pin is internally pulled low. This input pin is internally pulled low. This input pin is internally pulled low. 1. Not Active while in Host Mode 2. This input pin is internally pulled low. COMMENTS
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28
XRT75L03D THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.0 XRT75L03D PIN LISTING IN NUMERICAL ORDER
PIN # 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 PIN NAME RRING_1 RxAVDD_1 E3_1 REQEN_1 RLB_1 LLB_1 STS-1/DS3_1 LOSTHR AGND_2 RESET TEST RLOL_1 RLOS_1 EXDGND SFM_EN E3CLK/CLK_EN DS3CLK/ CLK_OUT STS-1CLK/12M EXDVDD RxDVDD_1 RPOS_1 RNEG_1/LCV_1 RCLK_1 RxDGND_1 AGND_1 JADGND JAGND_1 JADVDD JADVDD_1 REFAVDD RXA TYPE I *** I I I I I I *** I I O O *** I I I/O I *** *** O O O *** *** *** *** *** *** *** *** This input pin is internally pulled low. This input pin is internally pulled high. This input pin is internally pulled low. 1. Not Active while in Host Mode 2. This input pin is internally pulled low. 1. Not Active while in Host Mode 2. This input pin is internally pulled low. Not Active while in Host Mode Not Active while in Host Mode 1. Not Active while in Host Mode 2. This input pin is internally pulled low. COMMENTS
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29
XRT75L03D THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.0 XRT75L03D PIN LISTING IN NUMERICAL ORDER
PIN # 123 124 125 126 127 128 PIN NAME RXB REFGND TxON_2 TxAGND_1 DMO_1 TxAVDD_1 TYPE *** *** I *** O *** This input pin is internally pulled 'High'. COMMENTS
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30
XRT75L03D THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.0 1.0 ELECTRICAL CHARACTERISTICS TABLE 1: ABSOLUTE MAXIMUM RATINGS
SYMBOL
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PARAMETER Supply Voltage Input Voltage at any Pin Input current at any pin Storage Temperature Ambient Operating Temperature Thermal Resistance
MIN
MAX
UNITS
COMMENTS
VDD VIN IIN STEMP ATEMP Theta JA
-0.5 -0.5
6.0 5.5 100
V V mA
0
Note 1 Note 1 Note 1 Note 1 linear airflow 0 ft./min linear air flow 0ft/min (See Note 3 below)
-65 -40
150 85 23
0
C
0C
C/W
MLEVL
Exposure to Moisture
5
level
EIA/JEDEC JESD22-A112-A
ESD
ESD Rating
2000
V
Note 2
NOTES: 1. Exposure to or operating near the Min or Max values for extended period may cause permanent failure and impair reliability of the device. 2. ESD testing method is per MIL-STD-883D,M-3015.7 3. With Linear Air flow of 200 ft/min, reduce Theta JA by 20%, Theta JC is unchanged.
TABLE 2: DC ELECTRICAL CHARACTERISTICS:
SYMBOL
PARAMETER Digital Supply Voltage Analog Supply Voltage Supply current requirements Power Dissipation Input Low Voltage Input High Voltage Output Low Voltage, IOUT = - 4mA Output High Voltage, IOUT = 4 mA Input Leakage Current1 Input Capacitance Load Capacitance
MIN.
TYP.
MAX.
UNITS
DVDD AVDD ICC PDD VIL VIH VOL VOH IL CI CL
3.135 3.135
3.3 3.3 480 1.3
3.465 3.465 530 1.5 0.8
V V mA W V V V V
2.0
5.5 0.4
2.4 10 10 10
A pF pF
NOTES: 1. Not applicable for pins with pull-up or pull-down resistors. 2. The Digital inputs and outputs are TTL 5V compliant.
31
XRT75L03D THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.0 2.0 TIMING CHARACTERISTICS FIGURE 3. TYPICAL INTERFACE BETWEEN TERMINAL EQUIPMENT AND THE XRT75L03D (DUAL-RAIL DATA)
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TxPOS Terminal Equipment (E3/DS3 or STS-1 Framer) TxNEG TxLineClk
TPData TNData TxClk
Transmit Logic Block
Exar E3/DS3/STS-1 LIU
FIGURE 4. TRANSMITTER TERMINAL INPUT TIMING
tR T X tF T X
T xC lk
tT SU tT H O
T PD ata or T N D ata T TIP or T R ing
tT D Y
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
TxClk
Duty Cycle E3 DS3 STS-1
30
50 34.368 44.736 51.84
70
% MHz MHz MHz
tRTX tFTX tTSU tTHO tTDY
TxClk Rise Time (10% to 90%) TxClk Fall Time (10% to 90%) TPData/TNData to TxClk falling set up time TPData/TNData to TxClk falling hold time TTIP/TRing to TxClk rising propagation delay time 3 3 8
4 4
ns ns ns ns ns
32
XRT75L03D THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.0 FIGURE 5. RECEIVER DATA OUTPUT AND CODE VIOLATION TIMING
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t RRX RClk t LCVO LCV tC O RPOS or RNEG
t FRX
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
RxClk
Duty Cycle E3 DS3 STS-1
45
50 34.368 44.736 51.84 2 2
55
% MHz MHz MHz
tRRX tFRX tCO tLCVO
RxClk rise time (10% o 90%) RxClk falling time (10% to 90%) RxClk to RPOS/RNEG delay time RxClk to rising edge of LCV output delay
4 4 4
ns ns ns ns
2.5
FIGURE 6. TRANSMIT PULSE AMPLITUDE TEST CIRCUIT FOR E3, DS3 AND STS-1 RATES
TTIP(n)
37.4 +1%
37.4 + 1%
TxPOS(n) TxNEG(n) TxLineClk(n)
R2
TPData(n) TNData(n) TxClk(n)
R1
R3 75 1:1
TRing(n) XRT75L03D (0nly one channel shown)
33
XRT75L03D THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.0 3.0 LINE SIDE CHARACTERISTICS: 3.1 E3 line side parameters: The XRT75L03D line output at the transformer output meets the pulse shape specified in ITU-T G.703 for 34.368 Mbits/s operation. The pulse mask as specified in ITU-T G.703 for 34.368 Mbits/s is shown in Figure 7. FIGURE 7. PULSE MASK FOR E3 (34.368 MBITS/S) INTERFACE AS PER ITU-T G.703
17 ns (14.55 + 2.45)
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V = 100%
8.65 ns
Nominal Pulse
50%
14.55ns 12.1ns (14.55 - 2.45) 10% 20%
10% 0%
34
XRT75L03D THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.0 TABLE 3: E3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS
PARAMETER MIN TYP MAX UNITS
ac
TRANSMITTER LINE SIDE OUTPUT CHARACTERISTICS Transmit Output Pulse Amplitude (Measured at secondary of the transformer) Transmit Output Pulse Amplitude Ratio Transmit Output Pulse Width Transmit Intrinsic Jitter (without Jitter Attenuator in theTransmit path) Transmit Intrinsic Jitter ( with Jitter Attenuator in the Transmit path) RECEIVER LINE SIDE INPUT CHARACTERISTICS Receiver Sensitivity (length of cable) Interference Margin Jitter Tolerance @ Jitter Frequency 800KHz Signal level to Declare Loss of Signal Signal Level to Clear Loss of Signal Occurence of LOS to LOS Declaration Time Termination of LOS to LOS Clearance Time -15 10 10 255 255 900 -20 0.15 1200 -14 0.28 -35 feet dB UIPP dB dB UI UI 0.95 12.5 1.00 14.55 0.01 0.02 1.05 16.5 0.015 0.03 ns UIPP UIPP 0.9 1.0 1.1 Vpk
NOTE: The above values are at TA = 250C and VDD = 3.3 V 5%.
35
XRT75L03D THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.0 FIGURE 8. BELLCORE GR-253 CORE TRANSMIT OUTPUT PULSE TEMPLATE FOR SONET STS-1 APPLICATIONS
ac
S T S -1 P u ls e T em p la te
1.2
1
0.8
Norm a lize d Am plitude
0.6 Lower Curve Upper Curve 0.4
0.2
0
-0.2
0 -1 1 2 3 4 5 6 7 8 9 1 1 2 3 1. 9 8 7 6 5 4 3 2 1 0. 0. 0. 0. 0. 0. 0. 0. 0. 1. 1. -0 . -0 . -0 . -0 . -0 . -0 . -0 . -0 . -0 . 1. 4
Tim e , in UI
TABLE 4: STS-1 PULSE MASK EQUATIONS
TIME IN UNIT INTERVALS LOWER CURVE -0.85 < T < -0.38 -0.38 - 0.03 NORMALIZED AMPLITUDE
< T < 0.36
* T 0.5 1 + sin -- 1 + ---------- - 0.03 0.18 2
- 0.03 UPPER CURVE
0.36 < T < 1.4
-0.85 < T < -0.68 -0.68 < T < 0.26
0.03
* T 0.5 1 + sin -- 1 + ---------- + 0.03 2 0.34 0.1 + 0.61 x e-2.4[T-0.26]
0.26 < T < 1.4
36
XRT75L03D THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.0 TABLE 5: STS-1 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS (GR-253)
PARAMETER MIN TYP MAX UNITS
ac
TRANSMITTER LINE SIDE OUTPUT CHARACTERISTICS Transmit Output Pulse Amplitude (measured with TxLEV = 0) Transmit Output Pulse Amplitude (measured with TxLEV = 1) Transmit Output Pulse Width Transmit Output Pulse Amplitude Ratio Transmit Intrinsic Jitter ( without Jitter Attenuator in Transmit path) Transmit Intrinsic Jitter ( with Jitter Attenuator in Transmit path) RECEIVER LINE SIDE INPUT CHARACTERISTICS Receiver Sensitivity (length of cable) Jitter Tolerance @ Jitter Frequency 400 KHz Signal Level to Declare Loss of Signal Signal Level to Clear Loss of Signal 900 0.15 Refer to Table 10 Refer to Table 10 1100 feet UIpp 8.6 0.9 9.65 1.0 0.01 0.02 10.6 1.1 0.015 0.04 UIpp UIpp ns 0.9 1.0 1.1 Vpk 0.65 0.75 0.9 Vpk
NOTE: The above values are at TA = 250C and VDD = 3.3 V 5%.
37
XRT75L03D THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.0 FIGURE 9. TRANSMIT OUPUT PULSE TEMPLATE FOR DS3 AS PER BELLCORE GR-499
ac
D S 3 P u ls e T e m p la te
1.2
1
0.8
No rm a li z e d Am p litu d e
0.6 Lower Curve Upper Curve 0.4
0.2
0
-0.2
0 -1 1 2 3 4 5 6 7 8 9 1 1 2 3 1. .9 .8 .7 .6 .5 .4 .3 .2 .1 0. 0. 0. 0. 0. 0. 0. 0. 0. 1. 1. -0 -0 -0 -0 -0 -0 -0 -0 -0 1. 4
T im e , in UI
TABLE 6: DS3 PULSE MASK EQUATIONS
TIME IN UNIT INTERVALS LOWER CURVE -0.85 < T < -0.36 -0.36 - 0.03 NORMALIZED AMPLITUDE
< T < 0.36
* T 0.5 1 + sin -- 1 + ---------- - 0.03 0.18 2
- 0.03 UPPER CURVE
0.36 < T < 1.4
-0.85 < T < -0.68 -0.68 < T < 0.36
0.03
* T 0.5 1 + sin -- 1 + ---------- + 0.03 2 0.34 0.08 + 0.407 x e-1.84[T-0.36]
0.36 < T < 1.4
38
XRT75L03D THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.0 TABLE 7: DS3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS (GR-499)
PARAMETER MIN TYP MAX UNITS
ac
TRANSMITTER LINE SIDE OUTPUT CHARACTERISTICS Transmit Output Pulse Amplitude (measured with TxLEV = 0) Transmit Output Pulse Amplitude (measured with TxLEV = 1) Transmit Output Pulse Width Transmit Output Pulse Amplitude Ratio Transmit Intrinsic Jitter ( without Jitter Attenuator in Transmit path) Transmit Intrinsic Jitter ( withJitter Attenuator in Transmit path) RECEIVER LINE SIDE INPUT CHARACTERISTICS Receiver Sensitivity (length of cable) Jitter Tolerance @ 400 KHz (Cat II) Signal Level to Declare Loss of Signal Signal Level to Clear Loss of Signal 900 0.15 Refer to Table 10 Refer to Table 10 1100 feet UIpp 10.10 0.9 11.18 1.0 0.01 0.02 12.28 1.1 0.015 0.04 UIpp UIpp ns 0.9 1.0 1.1 Vpk 0.65 0.75 0.85 Vpk
NOTE: The above values are at TA = 250C and VDD = 3.3V 5%.
FIGURE 10. MICROPROCESSOR SERIAL INTERFACE STRUCTURE
CS
SClk
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SDI
R/W
A0
A1
A2
A3
A4
A5
0
D0
D1
D2
D3
D4
D5
D6
D7
High Z SDO
D0 D1 D2 D3 D4 D5 D6 D7
High Z
NOTE: If the R/W bit is set to "1", then this denotes a "READ" operation with the Microprocessor Serial Interface. Conversely, if the R/W bit is set to "0", then this denotes a "WRITE" operation.
39
XRT75L03D THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.0 FIGURE 11. TIMING DIAGRAM FOR THE MICROPROCESSOR SERIAL INTERFACE
t28 CS t21 t26 SCLK t22 SDI t23 R/W A0 A1 t24 t27 t25
ac
CS
SCLK t29 SDO Hi-Z D0 t30 D1 Hi-Z t32 D2 D7 t31
SDI
TABLE 8: MICROPROCESSOR SERIAL INTERFACE TIMINGS ( TA = 250C, VDD=3.3V 5% AND LOAD = 10PF)
SYMBOL t21 t22 t23 t24 t25 t26 t27 t28 t29 t30 t31 t32 PARAMETER CS Low to Rising Edge of SClk SDI to Rising Edge of SClk SDI to Rising Edge of SClk Hold Time SClk "Low" Time SClk "High" Time SClk Period Falling Edge of SClk to rising edge of CS CS Inactive Time Falling Edge of SClk to SDO Valid Time Falling Edge of SClk to SDO Invalid Time Rising edge of CS to High Z Rise/Fall time of SDO Output MIN. 5 5 5 50 50 100 0 50 20 10 25 5 TYP. MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns
40
XRT75L03D
REV. 1.0.0
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
ac
FUNCTIONAL DESCRIPTION:
Figure 1 shows the functional block diagram of the device. Each channel can be independently configured either by Hardware Mode or by Host Mode to support E3, DS3 or STS-1 modes. A detailed operation of each section is described below. Each channel consists of the following functional blocks: 4.0 THE TRANSMITTER SECTION: The Transmitter Section, within each Channel, accepts TTL/CMOS level signals from the Terminal Equipment in selectable data formats.
* Convert the CMOS level B3ZS or HDB3 encoded data into pulses with shapes that are compliant with the
various industry standard pulse template requirements. Figures 7, 8 and 9 illustrate the pulse template requirements.
* Encode the un-encoded NRZ data into either B3ZS format for (DS3 or STS-1) or HDB3 format (for E3) and
convert to pulses with shapes and width that are compliant with industry standard pulse template requirements. Figures 7, 8 and 9 illustrate the pulse template requirements.
* In Single-Rail or un-encoded Non-Return-to-Zero (NRZ) mode, data is input via TPData_n pins while
TNData_n pins must be grounded. The NRZ or Single-Rail mode is selected when the SR/DR input pin is "High" (in Hardware Mode) or bit 0 of channel control register is "1" (in Host Mode). Figure 12 illustrates the Single-Rail or NRZ format. FIGURE 12. SINGLE-RAIL OR NRZ DATA FORMAT (ENCODER AND DECODER ARE ENABLED)
Data
1
1
0
TPData TxClk
* In Dual-Rail mode, data is input via TPData_n and TNData_n pins. TPData_n contains positive data and
TNData_n contains negative data. The SR/DR input pin = "Low" (in Hardware Mode) or bit 0 of channel register = "0" (in Host Mode) enables the Dual-Rail mode. Figure 13 illustrates the Dual-Rail data format. FIGURE 13. DUAL-RAIL DATA FORMAT (ENCODER AND DECODER ARE DISABLED)
Data
1
1
0
TPData TNData TxClk
41
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER 4.1
ac
XRT75L03D
REV. 1.0.0
TRANSMIT CLOCK:
The Transmit Clock applied via TxClk_n pins, for the selected data rate (for E3 = 34.368 MHz, DS3 = 44.736 MHz or STS-1 = 51.84 MHz), is duty cycle corrected by the internal PLL circuit to provide a 50% duty cycle clock to the pulse shaping circuit. This allows a 30% to 70% duty cycle Transmit Clock to be supplied. 4.2
B3ZS/HDB3 ENCODER:
When the Single-Rail (NRZ) data format is selected, the Encoder Block encodes the data into either B3ZS format (for either DS3 or STS-1) or HDB3 format (for E3). 4.2.1 B3ZS Encoding: An example of B3ZS encoding is shown in Figure 14. If the encoder detects an occurrence of three consecutive zeros in the data stream, it is replaced with either B0V or 00V, where `B' refers to Bipolar pulse that is compliant with the Alternating polarity requirement of the AMI (Alternate Mark Inversion) line code and `V' refers to a Bipolar Violation (e.g., a bipolar pulse that violates the AMI line code). The substitution of B0V or 00V is made so that an odd number of bipolar pulses exist between any two consecutive violation (V) pulses. This avoids the introduction of a DC component into the line signal. FIGURE 14. B3ZS ENCODING FORMAT
TClk TPDATA Line Signal
1 1 0 0 1 11 1 0 0 1 0 0 V 0 0 B 0 0 0 V B 0 0 0 V 0
0 0
0 0
0 V
0 0
1
4.2.2
HDB3 Encoding:
An example of the HDB3 encoding is shown in Figure 15. If the HDB3 encoder detects an occurrence of four consecutive zeros in the data stream, then the four zeros are substituted with either 000V or B00V pattern. The substitution code is made in such a way that an odd number of bipolar (B) pulses exist between any consecutive V pulses. This avoids the introduction of DC component into the analog signal. FIGURE 15. HDB3 ENCODING FORMAT
TClk TPDATA Line Signal
1 1 0 0 1 11 1 0 0 0 0 0 0 0 V 1 1 0 0 0 0 0 0 V 0 0 B 0 0 0 0 0 V B 0
42
XRT75L03D
REV. 1.0.0
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
ac
NOTES: 1. When Dual-Rail data format is selected, the B3ZS/HDB3 Encoder is automatically disabled. 2. In Dual-Rail format, the Bipolar Violations in the incoming data stream is converted to valid data pulses. 3. Encoder and Decoder is enabled only in Single-Rail mode.
4.3
TRANSMIT PULSE SHAPER:
The Transmit Pulse Shaper converts the B3ZS encoded digital pulses into a single analog Alternate Mark Inversion (AMI) pulse that meet the industry standard mask template requirements for STS-1 and DS3. See Figures 8 and 9. For E3 mode, the pulse shaper converts the HDB3 encoded pulses into a single full amplitude square shaped pulse with very little slope. This is illustrated in Figure 7. The Pulse Shaper Block also includes a Transmit Build Out Circuit, which can either be disabled or enabled by setting the TxLEV_n input pin "High" or "Low" (in Hardware Mode) or setting the TxLEV_n bit to "1" or "0" in the control register (in Host Mode). For DS3/STS-1 rates, the Transmit Build Out Circuit is used to shape the transmit waveform that ensures that transmit pulse template requirements are met at the Cross-Connect system. The distance between the transmitter output and the Cross-Connect system can be between 0 to 450 feet. For E3 rate, since the output pulse template is measured at the secondary of the transformer and since there is no Cross-Connect system pulse template requirements, the Transmit Build Out Circuit is always disabled. 4.3.1 Guidelines for using Transmit Build Out Circuit: If the distance between the transmitter and the DSX3 or STSX-1, Cross-Connect system, is less than 225 feet, enable the Transmit Build Out Circuit by setting the TxLEV_n input pin "Low" (in Hardware Mode) or setting the TxLEV_n control bit to "0" (in Host Mode). If the distance between the transmitter and the DSX3 or STSX-1 is greater than 225 feet, disable the Transmit Build Out Circuit. 4.3.2 Interfacing to the line: The differential line driver increases the transmit waveform to appropriate level and drives into the 75 load as shown in Figure 6.
43
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER 4.4
ac
XRT75L03D
REV. 1.0.0
Transmit Drive Monitor:
This feature is used for monitoring the transmit line for occurrence of fault conditions such as a short circuit on the line or a defective line driver. To activate this function, connect MTIP_n pins to the TTIP_n lines via a 270 resistor and MRing_n pins to TRing_n lines via 270 resistor as shown in Figure 16. FIGURE 16. TRANSMIT DRIVER MONITOR SET-UP.
TTIP(n)
R1
37.4 +1%
TxPOS(n) TxNEG(n) TxLineClk(n)
TPData(n) TNData(n) TxClk(n) TRing(n)
MTIP(n) MRing(n)
R2
R3 75
37.4 + 1%
1:1
R4 270 R5 270
XRT75L03D (0nly one channel shown)
When the MTIP_n and MRing_n are connected to the TTIP_n and TRing_n lines, the drive monitor circuit monitors the line for transitions. The DMO_n (Drive Monitor Output) will be asserted "Low" as long as the transitions on the line are detected via MTIP_n and MRing_n. If no transitions on the line are detected for 128 32 TxClk_n periods, the DMO_n output toggles "High" and when the transitions are detected again, DMO_n toggles "Low".
NOTE: The Drive Monitor Circuit is only for diagnostic purpose and does not have to be used to operate the transmitter.
4.5
Transmitter Section On/Off:
The transmitter section of each channel can either be turned on or off. To turn on the transmitter, set the input pin TxON_n to "High" (in Hardware Mode) or write a "1" to the TxON_n control bits (in Host Mode) and TxON_n pins tied "High". When the transmitter is turned off, TTIP_n and TRing_n are tri-stated.
NOTES: 1. 2. This feature provides support for Redundancy. If the XRT75L03D is configured in Host mode, to permit a system designed for redundancy to quickly shut-off the defective line card and turn on the back-up line card, writing a "1" to the TxON_n control bits transfers the control to TxON_n pins.
5.0 THE RECEIVER SECTION: This section describes the detailed operation of the various blocks in the receiver. The receiver recovers the TTL/CMOS level data from the incoming bipolar B3ZS or HDB3 encoded input pulses. 5.1
AGC/Equalizer:
The Adaptive Gain Control circuit amplifies the incoming analog signal and compensates for the various flat losses and also for the loss at one-half symbol rate. The AGC has a dynamic range of 30 dB. The Equalizer restores the integrity of the signal and compensates for the frequency dependent attenuation of up to 900 feet of coaxial cable (1300 feet for E3). The Equalizer also boosts the high frequency content of the
44
XRT75L03D
REV. 1.0.0
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
ac
signal to reduce Inter-Symbol Interference (ISI) so that the slicer slices the signal at 50% of peak voltage to generate Positive and Negative data. The Equalizer can either be "IN" or "OUT" by setting the REQEN_n pin "High" or "Low" (in Hardware Mode) or setting the REQEN_n control bit to "1" or "0" (in Host Mode). RECOMMENDATIONS FOR EQUALIZER SETTINGS: The Equalizer has two gain settings to provide optimum equalization. In the case of normally shaped DS3/ STS-1 pulses (pulses that meet the template requirements) that has been driven through 0 to 900 feet of cable, the Equalizer can be left "IN" by setting the REQEN_n pin to "High" (in Hardware Mode) or setting the REQEN_n control bit to "1" (in Host Mode). However, for square-shaped pulses such as E3 or for DS3/STS-1 high pulses (that does not meet the pulse template requirements), it is recommended that the Equalizer be left "OUT" for cable length less than 300 feet by setting the REQEN_n pin "Low" (in Hardware Mode) or by setting the REQEN_n control bit to "0" (in Host Mode).This would help to prevent over-equalization of the signal and thus optimize the performance in terms of better jitter transfer characteristics.
NOTE: The results of extensive testing indicates that even when the Equalizer was left "IN" (REQEN_n = "HIGH"), regardless of the cable length, the integrity of the E3 signal was restored properly over 0 to 12 dB cable loss at Industrial Temperature.
The Equalizer also contain an additional 20 dB gain stage to provide the line monitoring capability of the resistively attenuated signals which may have 20dB flat loss. This capability can be turned on by writing a "1" to the RxMON_n bits in the control register or by setting the RxMON pin (pin 69) "High". 5.1.1 Interference Tolerance: For E3 mode, ITU-T G.703 Recommendation specifies that the receiver be able to recover error-free clock and data in the presence of a sinusoidal interfering tone signal. For DS3 and STS-1 modes, the same recommendation is being used. Figure 17 shows the configuration to test the interference margin for DS3/ STS1. Figure 18 shows the set up for E3. FIGURE 17. INTERFERENCE MARGIN TEST SET UP FOR DS3/STS-1
Atte n ua to r S ine W a ve G e n e ra to r N
0 to 9 00 feet C oaxial C ab le
DUT X R T7 5 L 0 3 D
Te st E quip m e nt
P a tte rn G e n e ra to r 2 23 -1 P R B S
S
D S 3 = 2 2.3 68 M H z S TS -1 = 2 5.9 2 M Hz
45
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER FIGURE 18. INTERFERENCE MARGIN TEST SET UP FOR E3.
A ttenuator 1
N o is e G e n e ra to r 2 2 3 -1 P R B S N
ac
XRT75L03D
REV. 1.0.0
A ttenuator 2
0 to 12 dB C a ble Lo ss
DUT X R T 75 L 03D
T est E quipm ent
S S ig n a l S o u rc e
TABLE 9: INTERFERENCE MARGIN TEST RESULTS
MODE CABLE LENGTH (ATTENUATION) INTERFERENCE TOLERANCE Equalizer "IN" E3 0 dB 12 dB 0 feet DS3 225 feet 450 feet 0 feet STS-1 225 feet 450 feet -17 dB -14 gB -15 dB -15 dB -14 dB -15 dB -14 dB -14 dB
5.2
Clock and Data Recovery:
The Clock and Data Recovery Circuit extracts the embedded clock, RxClk_n from the sliced digital data stream and provides the retimed data to the B3ZS (HDB3) decoder. The Clock Recovery PLL can be in one of the following two modes: TRAINING MODE: In the absence of input signals at RTIP_n and RRing_n pins, or when the frequency difference between the recovered line clock signal and the reference clock applied on the ExClk_n input pins exceed 0.5%, a Loss of Lock condition is declared by toggling RLOL_n output pin "High" (in Hardware Mode) or setting the RLOL_n bit to "1" in the control registers (in Host Mode). Also, the clock output on the RxClk_n pins are the same as the reference clock applied on ExClk_n pins. DATA/CLOCK RECOVERY MODE: In the presence of input line signals on the RTIP_n and RRing_n input pins and when the frequency difference between the recovered clock signal and the reference clock signal is less than 0.5%, the clock that is output on the RxClk_n out pins is the Recovered Clock signal.
46
XRT75L03D
REV. 1.0.0
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
ac
5.3
B3ZS/HDB3 Decoder:
The decoder block takes the output from clock and data recovery block and decodes the B3ZS (for DS3 or STS-1) or HDB3 (for E3) encoded line signal and detects any coding errors or excessive zeros in the data stream. Whenever the input signal violates the B3ZS or HDB3 coding sequence for bipolar violation or contains three (for B3ZS) or four (for HDB3) or more consecutive zeros, an active "High" pulse is generated on the RLCV_n output pins to indicate line code violation.
NOTE: In Dual-Rail mode, the decoder is bypassed.
5.4 5.4.1
LOS (Loss of Signal) Detector:
DS3/STS-1 LOS Condition:
A Digital Loss of SIgnal (DLOS) condition occurs when a string of 175 75 consecutive zeros occur on the line. When the DLOS condition occurs, the DLOS_n bit is set to "1" in the status control register. DLOS condition is cleared when the detected average pulse density is greater than 33% for 175 75 pulses. Analog Loss of Signal (ALOS) condition occurs when the amplitude of the incoming line signal is below the threshold as shown in the Table 10.The status of the ALOS condition is reflected in the ALOS_n status control register. RLOS is the logical OR of the DLOS and ALOS states. When the RLOS condition occurs the RLOS_n output pin is toggled "High" and the RLOS_n bit is set to "1" in the status control register. TABLE 10: THE ALOS (ANALOG LOS) DECLARATION AND CLEARANCE THRESHOLDS FOR A GIVEN SETTING OF LOSTHR AND REQEN (DS3 AND STS-1 APPLICATIONS)
APPLICATION REQEN SETTING LOSTHR SETTING DS3 0 1 0 1 STS-1 0 1 0 1 0 0 1 1 0 0 1 1 SIGNAL LEVEL TO DECLARE ALOS DEFECT < 75mVpk < 45mVpk < 120mVpk < 55mVpk < 120mVpk < 50mVpk < 125mVpk < 55mVpk SIGNAL LEVEL TO CLEAR ALOS DEFECT > 130mVpk > 60mVpk > 45mVpk > 180mVpk > 170mVpk > 75mVpk > 205mVpk > 90mVpk
DISABLING ALOS/DLOS DETECTION: For debugging purposes it is useful to disable the ALOS and/or DLOS detection. Writing a "1" to both ALOSDIS_n and DLOSDIS_n bits disables the LOS detection on a per channel basis. 5.4.2 E3 LOS Condition: If the level of incoming line signal drops below the threshold as described in the ITU-T G.775 standard, the LOS condition is detected. Loss of signal level is defined to be between 15 and 35 dB below the normal level. If the signal drops below 35 dB for 10 to 255 consecutive pulse periods, LOS condition is declared. This is illustrated in Figure 19.
47
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER FIGURE 19. LOSS OF SIGNAL DEFINITION FOR E3 AS PER ITU-T G.775
0 dB
ac
XRT75L03D
REV. 1.0.0
Maximum Cable Loss for E3
LOS Signal Must be Cleared
-12 dB -15dB
LOS Signal may be Cleared or Declared
-35dB
LOS Signal Must be Declared
As defined in ITU-T G.775, an LOS condition is also declared between 10 and 255 UI (or E3 bit periods) after the actual time the LOS condition has occurred. The LOS condition is cleared within 10 to 255 UI after restoration of the incoming line signal. Figure 20 shows the LOS declaration and clearance conditions. FIGURE 20. LOSS OF SIGNAL DEFINITION FOR E3 AS PER ITU-T G.775.
Actual Occurrence of LOS Condition RTIP/ RRing Line Signal is Restored
10 UI
255 UI
Time Range for LOS Declaration
10 UI
255 UI
RLOS Output Pin 0 UI G.775 Compliance 0 UI Time Range for LOS Clearance G.775 Compliance
48
XRT75L03D
REV. 1.0.0
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER Muting the Recovered Data with LOS condition:
ac
5.4.3
When the LOS condition is declared, the clock recovery circuit locks into the reference clock applied to the ExClk_n pin and output this clock on the RxClk_n output.In Single Frequency Mode (SFM), the clock recovery locks into the rate clock generated and output this clock on the RxClk_n pins. The data on the RPOS_n and RNEG_n pins can be forced to zero by pulling the LOSMUT pin "High" (in Hardware Mode) or by setting the LOSMUT_n bits in the individual channel control register to "1" (in Host Mode).
NOTE: When the LOS condition is cleared, the recovered data is output on RPOS_n and RNEG_n pins.
6.0 JITTER: There are three fundamental parameters that describe circuit performance relative to jitter:
* Jitter Tolerance (Receiver) * Jitter Transfer (Receiver/Transmitter) * Jitter Generation
6.1
JITTER TOLERANCE - RECEIVER:
Jitter tolerance is a measure of how well a Clock and Data Recovery unit can successfully recover data in the presence of various forms of jitter. It is characterized by the amount of jitter required to produce a specified bit error rate. The tolerance depends on the frequency content of the jitter. Jitter Tolerance is measured as the jitter amplitude over a jitter spectrum for which the clock and data recovery unit achieves a specified bit error rate (BER). To measure the jitter tolerance as shown in Figure 21, jitter is introduced by the sinusoidal modulation of the serial data bit sequence. FIGURE 21. JITTER TOLERANCE MEASUREMENTS
P atte rn G en erato r
D a ta
DUT X R T7 5L 03 D
E rro r D etec to r
C lo c k M o d u la tio n F re q .
FREQ S yn th e sizer
Input jitter tolerance requirements are specified in terms of compliance with jitter mask which is represented as a combination of points.Each point corresponds to a minimum amplitude of sinusoidal jitter at a given jitter frequency. 6.1.1 DS3/STS-1 Jitter Tolerance Requirements: Bellcore GR-499 CORE, Issue 1, December 1995 specifies the minimum requirement of jitter tolerance for Category I and Category II. The jitter tolerance requirement for Category II is the most stringent. Figure 22 shows the jitter tolerance curve as per GR-499 specification.
49
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER FIGURE 22. INPUT JITTER TOLERANCE FOR DS3/STS-1
ac
XRT75L03D
REV. 1.0.0
64 41 15 J IT T E R A M P L IT U D E (UpI) p
G R -2 5 3 G R -4 9 9 G R -4 9 9
S T S -1 C a t II Cat I
10 5
XR T75L03D
1 .5 0 .3 0 .1 5 0 .1
0 .0 1
0 .0 3
0 .3
2
20
100
J IT T E R F R E Q U E N C Y (k H z )
6.1.2
E3 Jitter Tolerance Requirements:
ITU-T G.823 standard specifies that the clock and data recovery unit must be able to accommodate and tolerate jitter up to certain specified limits. Figure 23 shows the tolerance curve. FIGURE 23. INPUT JITTER TOLERANCE FOR E3
64 J IT T E R A M P L IT U D E (UpI) p 10
IT U -T G .8 2 3 XRT75L03D
1 .5
0 .3
0 .1
1 J IT T E R F R E Q U E N C Y (k H z )
10
800
As shown in the Figures 22 and 23 above, in the jitter tolerance measurement, the dark line indicates the minimum level of jitter that the E3/DS3/STS-1 compliant component must tolerate. The Table 11 below shows the jitter amplitude versus the modulation frequency for various standards.
50
XRT75L03D
REV. 1.0.0
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER TABLE 11: JITTER AMPLITUDE VERSUS MODULATION FREQUENCY (JITTER TOLERANCE)
ac
BIT RATE (KB/S) 34368 44736 44736 51840
INPUT JITTER AMPLITUDE (UI P-P) STANDARD A1 ITU-T G.823 GR-499 CORE Cat I GR-499 CORE Cat II GR-253 CORE Cat II 1.5 5 10 15 A2 0.15 0.1 0.3 1.5 A3 0.15
F1(HZ)
MODULATION FREQUENCY
F2(HZ) F3(KHZ) F4(KHZ) F5(KHZ)
100 10 10 10
1000 2.3k 669 30
10 60 22.3 300
800 300 300 2
20
6.2
JITTER TRANSFER - RECEIVER/TRANSMITTER:
Jitter Transfer function is defined as the ratio of jitter on the output relative to the jitter applied on the input versus frequency. There are two distinct characteristics in jitter transfer: jitter gain (jitter peaking) defined as the highest ratio above 0dB; and jitter transfer bandwidth.The overall jitter transfer bandwidth is controlled by a low bandwidth loop, typically using a voltage-controller crystal oscillator (VCXO). The jitter transfer function is a ratio between the jitter output and jitter input for a component, or system often expressed in dB. A negative dB jitter transfer indicates the element removed jitter. A positive dB jitter transfer indicates the element added jitter.A zero dB jitter transfer indicates the element had no effect on jitter. Table 12 shows the jitter transfer characteristics and/or jitter attenuation specifications for various data rates: TABLE 12: JITTER TRANSFER SPECIFICATION/REFERENCES
E3 ETSI TBR-24 DS3 GR-499 CORE section 7.3.2 Category I and Category II STS-1 GR-253 CORE section 5.6.2.1
The above specifications can be met only with a jitter attenuator that supports E3/DS3/STS-1 rates. 6.3
Jitter Attenuator:
An advanced crystal-less jitter attenuator per channel is included in the XRT75L03D. The jitter attenuator requires no external crystal nor high-frequency reference clock. In Host mode, by clearing or setting the JATx/Rx_n bits in the channel control registers selects the jitter attenuator either in the Receive or Transmit path on per channel basis. In Hardware mode, JATx/Rx pin selects globally all three channels either in Receive or Transmit path. The FIFO size can be either 16-bit or 32-bit. In HOST mode, the bits JA0_n and JA1_n can be set to appropriate combination to select the different FIFO sizes or to disable the Jitter Attenuator on a per channel basis. In Hardware mode, appropriate setting of the pins JA0 and JA1 selects the different FIFO sizes or disables the Jitter Attenuator for all three channels. Data is clocked into the FIFO with the associated clock signal (TxClk or RxClk) and clocked out of the FIFO with the dejittered clock. When the FIFO is within two bits of overflowing or underflowing, the FIFO limit status bit, FL_n is set to "1" in the Alarm status register. Reading this bit clears the FIFO and resets the bit into default state.
NOTE: It is recommended to select the 16-bit FIFO for delay-sensitive applications as well as for removing smaller amounts of jitter. Table 13 specifies the jitter transfer mask requirements for various data rates:
51
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER TABLE 13: JITTER TRANSFER PASS MASKS
RATE (KBITS) 34368 44736 MASK G.823 ETSI-TBR-24 GR-499, Cat I GR-499, Cat II GR-253 CORE GR-253 CORE F1 (HZ) 100 F2 (HZ) 300 F3 (HZ) 3K F4 (KHZ) 800K A1(dB) 0.5
ac
XRT75L03D
REV. 1.0.0
A2(dB) -19.5
10 10 10 10
10k 56.6k 40 40k
-
15k 300k 15k 400k
0.1 0.1 0.1 0.1
-
51840
The jitter attenuator within the XRT75L03D meets the latest jitter attenuation specifications and/or jitter transfer characteristics as shown in the Figure 24. FIGURE 24. JITTER TRANSFER REQUIREMENTS AND JITTER ATTENUATOR PERFORMANCE
J IT T E R A M P L IT U D E
A1 A2
F1
F2
F3
F4
J IT T E R F R E Q U E N C Y ( k H z )
6.3.1
JITTER GENERATION:
Jitter Generation is defined as the process whereby jitter appears at the output port of the digital equipment in the absence of applied input jitter. Jitter Generation is measured by sending jitter free data to the clock and data recovery circuit and measuring the amount of jitter on the output clock or the re-timed data. Since this is essentially a noise measurement, it requires a definition of bandwidth to be meaningful. The bandwidth is set according to the data rate. In general, the jitter is measured over a band of frequencies. 7.0 SERIAL HOST INTERFACE: A serial microprocessor interface is included in the XRT75L03D. The interface is generic and is designed to support the common microprocessors/microcontrollers. The XRT75L03D operates in Host mode when the HOST/HW pin is tied "High". The serial interface includes a serial clock (SClk), serial data input (SDI), serial data output (SDO), chip select (CS) and interrupt output (INT). The serial interface timing is shown in Figure 11. The active low interrupt output signal (INT pin) indicates alarm conditions like LOS, DMO and FL to the processor.
52
XRT75L03D
REV. 1.0.0
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
ac
When the XRT75L03D is configured in Host mode, the following input pins,TxLEV_n, TAOS_n, RLB_n, LLB_n, E3_n, STS-1/DS3_n, REQEN_n, JATx/Rx, JA0 and JA1 are disabled and must be connected to ground. The Table 14 below illustrates the functions of the shared pins in either Host mode or in Hardware mode. TABLE 14: FUNCTIONS OF SHARED PINS
PIN NUMBER 66 67 68 69 71 IN HOST MODE CS SClk SDI SDO INT IN HARDWARE MODE RxClkINV TxClkINV RxON RxMON LOSMUT
NOTE: While configured in Host mode, the TxON_n input pins will be active if the TxON_n bits in the control register are set to "1", and can be used to turn on and off the transmit output drivers. This permits a system designed for redundancy to quickly switch out a defective line card and switch-in the backup line card.
53
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER TABLE 15: XRT75L03D REGISTER MAP - QUICK LOOK
ADDRESS LOCATION 0x00 REGISTER NAME APS/Redundancy Control Register BIT 7 Reserved BIT 6 BIT 5 BIT 4 BIT 3 Reserved BIT 2 BIT 1
ac
XRT75L03D
REV. 1.0.0
BIT 0
RxON Ch 2 RxON Ch 1 RxON Ch 0
TxON Ch 2 TxON Ch 1 TxON Ch 0
CHANNEL 0 REGISTERS 0x01 Source Level Interrupt Enable Register - Ch 0 Reserved Change of FL Alarm Condition Interrupt Enable Change of RLOL Condition Interrupt Enable Change of RLOS Defect Condition Interrupt Enable Change of RLOS Condition Interrupt Status RLOS Defect Condition TxCLK INV Change of DMO Condition Interrupt Enable
0x02
Source Level Interrupt Status Register - Ch 0
Reserved
Change of FL Alarm Condition Interrupt Status ALOS Defect Declared Insert PRBS Error FL Alarm Declared
Change of RLOL Condition Interrupt Status RLOL Condition Declared TAOS
Change of DMO Condition Interrupt Status DMO Condition Status TxLEV
0x03
Alarm Status Register - Ch 0
Reserved
Loss of PRBS Pattern Sync
DLOS Defect Declared Internal Transmit Drive Monitoring DisableDLOS Detector
0x04
Transmit Control Register - Ch 0
Reserved
Unused
0x05
Receive Control Register - Ch 0
Reserved
DisableALOS Detector
RxCLK INV
LOSMUTEnable
Receive Monitor Mode Enable STS-1/DS3 Mode JA in TxPath
Receive Equalizer Enable
0x06
Channel Control Register - Ch 0 Jitter Attenuator Control Register Ch 0
Reserved
PRBS Enable
RLB
LLB
E3 Mode
SR/DR Mode JA0 (JA Mode Select 0)
0x07
Reserved
SONET APS Recovery Time Mode Disable CHANNEL 1 REGISTERS
JA RESET
JA1 (JA Mode Select Bit 1)
0x08 0x09
Reserved Source Level Interrupt Enable Register - Ch 0
Reserved Reserved
Reserved
Reserved Change of FL Alarm Condition Interrupt Enable
Reserved Change of RLOL Condition Interrupt Enable
Reserved Change of RLOS Defect Condition Interrupt Enable Change of RLOS Condition Interrupt Status
Reserved Change of DMO Condition Interrupt Enable
0x0A
Source Level Interrupt Status Register - Ch 0
Reserved
Change of FL Alarm Condition Interrupt Status
Change of RLOL Condition Interrupt Status
Change of DMO Condition Interrupt Status
54
XRT75L03D
REV. 1.0.0
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER TABLE 15: XRT75L03D REGISTER MAP - QUICK LOOK
ac
ADDRESS LOCATION 0x0B
REGISTER NAME Alarm Status Register - Ch 0
BIT 7 Reserved
BIT 6 Loss of PRBS Pattern Sync
BIT 5 DLOS Defect Declared Internal Transmit Drive Monitoring DisableDLOS Detector
BIT 4 ALOS Defect Declared Insert PRBS Error
BIT 3 FL Alarm Declared
BIT 2 RLOL Condition Declared TAOS
BIT 1 RLOS Defect Condition TxCLK INV
BIT 0 DMO Condition Status TxLEV
0x0C
Transmit Control Register - Ch 0
Reserved
Unused
0x0D
Receive Control Register - Ch 0
Reserved
DisableALOS Detector
RxCLK INV
LOSMUTEnable
Receive Monitor Mode Enable STS-1/DS3 Mode JA in TxPath
Receive Equalizer Enable
0x0E
Channel Control Register - Ch 0 Jitter Attenuator Control Register Ch 0
Reserved
PRBS Enable
RLB
LLB
E3 Mode
SR/DR Mode JA0 (JA Mode Select 0)
0x0F
Reserved
SONET APS Recovery Time Mode Disable CHANNEL 2 REGISTERS
JA RESET
JA1 (JA Mode Select Bit 1)
0x10 0x11
Reserved Source Level Interrupt Enable Register - Ch 0
Reserved Reserved
Reserved
Reserved Change of FL Alarm Condition Interrupt Enable
Reserved Change of RLOL Condition Interrupt Enable
Reserved Change of RLOS Defect Condition Interrupt Enable Change of RLOS Condition Interrupt Status RLOS Defect Condition TxCLK INV
Reserved Change of DMO Condition Interrupt Enable
0x12
Source Level Interrupt Status Register - Ch 0
Reserved
Change of FL Alarm Condition Interrupt Status ALOS Defect Declared Insert PRBS Error FL Alarm Declared
Change of RLOL Condition Interrupt Status RLOL Condition Declared TAOS
Change of DMO Condition Interrupt Status DMO Condition Status TxLEV
0x13
Alarm Status Register - Ch 0
Reserved
Loss of PRBS Pattern Sync
DLOS Defect Declared Internal Transmit Drive Monitoring DisableDLOS Detector
0x14
Transmit Control Register - Ch 0
Reserved
Unused
0x15
Receive Control Register - Ch 0
Reserved
DisableALOS Detector
RxCLK INV
LOSMUTEnable
Receive Monitor Mode Enable STS-1/DS3 Mode
Receive Equalizer Enable
0x16
Channel Control Register - Ch 0
Reserved
PRBS Enable
RLB
LLB
E3 Mode
SR/DR Mode
55
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER TABLE 15: XRT75L03D REGISTER MAP - QUICK LOOK
ADDRESS LOCATION 0x17 REGISTER NAME Jitter Attenuator Control Register Ch 0 BIT 7 BIT 6 Reserved BIT 5 BIT 4 SONET APS Recovery Time Mode Disable BIT 3 JA RESET BIT 2 JA1 (JA Mode Select Bit 1) BIT 1 JA in TxPath
ac
XRT75L03D
REV. 1.0.0
BIT 0 JA0 (JA Mode Select 0)
0x19 0x1F 0x20
Reserved
Reserved
Block Level Interrupt Enable Register - Ch 32 Block Level Interrupt Enable Register - Ch 33 Reserved Reserved
0x21
0x22 0x3D 0x3E
Device Part Number Register Chip Revision Number Register Reserved
0
1
1
1
0
0
1
1
0x3F
0
0
0
0
Revision Number Value
0x40 0xFF
Reserved
LEGEND:
Denotes Reserved (or Unused) Register Bits Denotes Read/Write Bits Denotes Read-Only Bits Denotes Reset-Upon-Read Bits
THE REGISTER MAP AND DESCRIPTION FOR THE XRT75L03D 3-CHANNEL DS3/E3/STS-1 LIU IC TABLE 16: COMMAND REGISTER ADDRESS MAP, WITHIN THE XRT75L03D 3-CHANNEL DS3/E3/STS-1 LIU W/ JITTER ATTENUATOR IC
ADDRESS 0x00 COMMAND REGISTER CR0 TYPE R/W REGISTER NAME APS/Redundancy Control Register
CHANNEL 0 CONTROL REGISTERS 0x01 0x02 0x03 CR1 CR2 CR3 R/O R/W R/O Source Level Interrupt Enable Register - Channel 0 Source Level Interrupt Status Register Channel 0 Alarm Status Register - Channel 0
56
XRT75L03D
REV. 1.0.0
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
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TABLE 16: COMMAND REGISTER ADDRESS MAP, WITHIN THE XRT75L03D 3-CHANNEL DS3/E3/STS-1 LIU W/ JITTER ATTENUATOR IC
ADDRESS 0x04 0x05 0x06 0x07 COMMAND REGISTER CR4 CR5 CR6 CR7 TYPE R/W R/W R/W R/W REGISTER NAME Transmit Control Register - Channel 0 Receive Control Register - Channel 0 Channel Control Register - Channel 0 Jitter Attenuator Control Register - Channel 0
CHANNEL 1 CONTROL REGISTERS 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F CR8 CR9 CR10 CR11 CR12 CR13 CR14 CR15 R/O R/W RUR R/O R/W R/W R/W R/W Reserved Source Level Interrupt Enable Register - Channel 1 Source Level Interrupt Status Register - Channel 1 Alarm Status Register - Channel 1 Transmit Control Register - Channel 1 Receive Control Register - Channel 1 Channel Control Register - Channel 1 Jitter Attenuator Control Register - Channel 1
CHANNEL 2 CONTROL REGISTERS 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 - 0x1F CR16 CR17 CR18 CR19 CR20 CR21 CR22 CR23 Reserved BLOCK LEVEL INTERRUPT ENABLE/STATUS REGISTERS (CHANNELS 0 - 2) 0x20 0x21 0x22 - 0x3D CR32 CR33 Reserved R/W R/O Block Level Interrupt Enable Register Block Level Interrupt Status Register Reserved DEVICE IDENTIFICATION REGISTERS 0x3E 0x3F CR62 CR63 R/O R/O Device Part Number Register Chip Revision Number Register R/W R/W RUR R/O R/W R/W R/W R/W Reserved Source Level Interrupt Enable Register - Channel 2 Source Level Interrupt Status Register - Channel 2 Alarm Status Register - Channel 2 Transmit Control Register - Channel 2 Receive Control Register - Channel 2 Channel Control Register - Channel 2 Jitter Attenuator Control Register - Channel 2
57
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER THE GLOBAL/CHIP-LEVEL REGISTERS
ac
XRT75L03D
REV. 1.0.0
The register set, within the XRT75L03D consists of five "Global" or "Chip-Level" Registers and 21 per-Channel Registers. This section will present detailed information on the Global Registers. TABLE 17: LIST AND ADDRESS LOCATIONS OF GLOBAL REGISTERS
ADDRESS 0x00 0x01 - 0x1F 0x20 0x21 0x22 - 0x3D 0x3E 0x3F COMMAND REGISTER CR0 Bank of Per-Channel Registers CR32 CR33 Reserved Registers CR62 CR63 R/O R/O Device/Part Number Register Chip Revision Number Register R/W R/O Block Level Interrupt Enable Register Block Level Interrupt Status Register TYPE R/W REGISTER NAME APS/Redundancy Control Register
REGISTER DESCRIPTION - GLOBAL REGISTERS TABLE 18: APS/REDUNDANCY CONTROL REGISTER - CR0 (ADDRESS LOCATION = 0X00)
BIT 7 Reserved R/O 0 BIT 6 RxONCh 2 R/W 0 BIT 5 RxON Ch 1 R/W 0 BIT 4 RxON Ch 0 R/W 0 BIT 3 Reserved R/O 0 BIT 2 TxON Ch 2 R/W 0 BIT 1 TxON Ch 1 R/W 0 BIT 0 TxON Ch 0 R/W 0
BIT NUMBER 7 6
NAME Reserved RxON Ch 2
TYPE R/O R/W 0 0
DEFAULT VALUE
DESCRIPTION
Receiver Section ON - Channel 2 This READ/WRITE bit-field is used to either turn on or turn off the Receive Section of Channel 2. If the user turns on the Receive Section, then Channel 2 will begin to receive the incoming DS3, E3 or STS-1 data-stream via the RTIP_2 and RRING_2 input pins. Conversely, if the user turns off the Receive Section, then the entire Receive Section (e.g., AGC and Receive Equalizer Block, Clock Recovery PLL, etc) will be powered down. 0 - Shuts off the Receive Section of Channel 2. 1 - Turns on the Receive Section of Channel 2.
58
XRT75L03D
REV. 1.0.0
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
NAME RxON Ch 1 TYPE R/W 0 DEFAULT VALUE DESCRIPTION Receiver Section ON - Channel 1 This READ/WRITE bit-field is used to either turn on or turn off the Receive Section of Channel 1. If the user turns on the Receive Section, then Channel 1 will begin to receive the incoming DS3, E3 or STS-1 data-stream via the RTIP_1 and RRING_1 input pins. Conversely, if the user turns off the Receive Section, then the entire Receive Section (e.g., AGC and Receive Equalizer Block, Clock Recovery PLL, etc) will be powered down. 0 - Shuts off the Receive Section of Channel 1. 1 - Turns on the Receive Section of Channel 1. Receiver Section ON - Channel 0 This READ/WRITE bit-field is used to either turn on or turn off the Receive Section of Channel 0. If the user turns on the Receive Section, then Channel 0 will begin to receive the incoming DS3, E3 or STS-1 data-stream via the RTIP_0 and RRING_0 input pins. Conversely, if the user turns off the Receive Section, then the entire Receive Section (e.g., AGC and Receive Equalizer Block, Clock Recovery PLL, etc) will be powered down. 0 - Shuts off the Receive Section of Channel 0. 1 - Turns on the Receive Section of Channel 0.
ac
BIT NUMBER 5
4
RxON Ch 0
R/W
0
3 2
Reserved TxON Ch 2
R/O R/W
0 0 Transmit Driver ON - Channel 2 This READ/WRITE bit-field is used to either turn on or turn off the Transmit Driver associated with Channel 2. If the user turns on the Transmit Driver, then Channel 2 will begin to transmit DS3, E3 or STS-1 pulses on the line via the TTIP_2 and TRING_ 2 output pins. Conversely, if the user turns off the Transmit Driver, then the TTIP_2 and TRING_2 output pins will be tri-stated. 0 - Shuts off the Transmit Driver associated with Channel 2 and tristates the TTIP_2 and TRING_ 2 output pins. 1 - Turns on or enables the Transmit Driver associated with Channel 2.
NOTE: If the user wishes to exercise software control over the state of the Transmit Driver associated with Channel 2, then it is imperative that the user pull the TxON_2 (pin 125) to a logic "High" level.
59
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
BIT NUMBER 1 NAME TxON Ch 1 TYPE R/W 0 DEFAULT VALUE DESCRIPTION
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XRT75L03D
REV. 1.0.0
Transmit Section ON - Channel 1 This READ/WRITE bit-field is used to either turn on or turn off the Transmit Driver associated with Channel 1. If the user turns on the Transmit Driver, then Channel 1 will begin to transmit DS3, E3 or STS-1 pulses on the line via the TTIP_1 and TRING_ 1 output pins. Conversely, if the user turns off the Transmit Driver, then the TTIP_1 and TRING_1 output pins will be tri-stated. 0 - Shuts off the Transmit Driver associated with Channel 1 and tristates the TTIP_1 and TRING_ 1 output pins. 1 - Turns on or enables the Transmit Driver associated with Channel 1.
NOTE: If the user wishes to exercise software control over the state of the Transmit Driver associated with Channel 1, then it is imperative that the user pull the TxON_1 (pin 1) to a logic "High" level.
0 TxON Ch 0 R/W 0 Transmit Section ON - Channel 0 This READ/WRITE bit-field is used to either turn on or turn off the Transmit Driver associated with Channel 0. If the user turns on the Transmit Driver, then Channel 0 will begin to transmit DS3, E3 or STS-1 pulses on the line via the TTIP_0 and TRING_ 0 output pins. Conversely, if the user turns off the Transmit Driver, then the TTIP_0 and TRING_0 output pins will be tri-stated. 0 - Shuts off the Transmit Driver associated with Channel 0 and tristates the TTIP_0 and TRING_ 0 output pins. 1 - Turns on or enables the Transmit Driver associated with Channel 0.
NOTE: If the user wishes to exercise software control over the state of the Transmit Driver associated with Channel 0, then it is imperative that the user pull the TxON_0 (pin 38) to a logic "High" level.
60
XRT75L03D
REV. 1.0.0
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER TABLE 19: BLOCK LEVEL INTERRUPT ENABLE REGISTER - CR32 (ADDRESS LOCATION = 0X20)
ac
BIT 7
BIT 6
BIT 5 Reserved
BIT 4
BIT 3
BIT 2 Channel 2 Interrupt Enable
BIT 1 Channel 1 Interrupt Enable R/W 0
BIT 0 Channel 0 Interrupt Enable R/W 0
R/O 0
R/O 0
R/O 0
R/O 0
R/O 0
R/W 0
BIT NUMBER 7-3 2
NAME Unused Channel 2 Interrupt Enable
TYPE R/O R/W
DEFAULT VALUE 0 0
DESCRIPTION
Channel 2 Interrupt Enable Bit: This READ/WRITE bit-field is used to do either of the following
* To enable Channel 2 for Interrupt Generation at the Block Level * To disable all Interrupts associated with Channel 2 within the
XRT75L03D If the user enables Channel 2-related Interrupts at the Block Level, then this means that a given Channel 2-related interrupt (e.g., Change in LOS Defect Condition - Channel 2) will be enabled if the user has also enabled this particular interrupt at the Source Level. If the user disables Channel 2-related Interrupts at the Block Level, then this means that the XRT75L03D will NOT generate any Channel 2-Related Interrupts at all. 0 - Disables all Channel 2-related Interrupt. 1 - Enables Channel 2-related Interrupts at the Block Level. The user must still enable individual Channel 2-related Interrupts at the source level, before they are enabled for interrupt generation. 1 Channel 1 Interrupt Enable Channel 0 Interrupt Enable R/W 0 Channel 1 Interrupt Enable Bit: Please see the description for Bit 2 Channel 2 Interrupt Enable. Channel 0 Interrupt Enable Bit: Please see the description for Bit 2 Channel 2 Interrupt Enable.
0
R/W
0
61
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER TABLE 20: BLOCK LEVEL INTERRUPT STATUS REGISTER - CR33 (ADDRESS LOCATION = 0X21)
BIT 7 BIT 6 BIT 5 Reserved R/O 0 R/O 0 R/O 0 R/O 0 R/O 0 BIT 4 BIT 3 BIT 2 BIT 1
ac
XRT75L03D
REV. 1.0.0
BIT 0
Channel 2 Channel 1 Channel 0 Interrupt Status Interrupt Status Interrupt Status R/O 0 R/O 0 R/O 0
BIT NUMBER 7-3 2
NAME Unused Channel 2 Interrupt Status
TYPE R/O R/O
DEFAULT VALUE 0 0
DESCRIPTION
Channel 2 Interrupt Status Bit: This READ-ONLY bit-field indicates whether or not the XRT75L03D has a pending Channel 2-related interrupt that is awaiting service. 0 - Indicates that there is NO Channel 2-related Interrupt awaiting service. 1 - Indicates that there is at least one Channel 2-related Interrupt awaiting service. In this case, the user's Interrupt Service routine should be written such that the Microprocessor will now proceed to read out the contents of the Source Level Interrupt Status Register Channel 2 (Address Location = 0x12) in order to determine the exact cause of the interrupt request.
NOTE: Once this bit-field is set to "1", it will not be cleared back to "0" until the user has read out the contents of the SourceLevel Interrupt Status Register bit, that corresponds with the interrupt request.
62
XRT75L03D
REV. 1.0.0
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
NAME Channel 1 Interrupt Enable TYPE R/W DEFAULT VALUE 0 DESCRIPTION Channel 1 Interrupt Enable Bit: This READ-ONLY bit-field indicates whether or not the XRT75L03D has a pending Channel 1-related interrupt that is awaiting service. 0 - Indicates that there is NO Channel 1-related Interrupt awaiting service. 1 - Indicates that there is at least one Channel 1-related Interrupt awaiting service. In this case, the user's Interrupt Service routine should be written such that the Microprocessor will now proceed to read out the contents of the Source Level Interrupt Status Register Channel 1 (Address Location = 0x0A) in order to determine the exact cause of the interrupt request.
ac
BIT NUMBER 1
NOTE: Once this bit-field is set to "1", it will not be cleared back to "0" until the user has read out the contents of the SourceLevel Interrupt Status Register bit, that corresponds with the interrupt request.
0 Channel 0 Interrupt Enable R/W 0 Channel 0 Interrupt Enable Bit: This READ-ONLY bit-field indicates whether or not the XRT75L03D has a pending Channel 0-related interrupt that is awaiting service. 0 - Indicates that there is NO Channel 0-related Interrupt awaiting service. 1 - Indicates that there is at least one Channel 0-related Interrupt awaiting service. In this case, the user's Interrupt Service routine should be written such that the Microprocessor will now proceed to read out the contents of the Source Level Interrupt Status Register Channel 0 (Address Location = 0x02) in order to determine the exact cause of the interrupt request.
NOTE: Once this bit-field is set to "1", it will not be cleared back to "0" until the user has read out the contents of the SourceLevel Interrupt Status Register bit, that corresponds with the interrupt request.
TABLE 21: DEVICE/PART NUMBER REGISTER - CR62 (ADDRESS LOCATION = 0X3E)
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Part Number ID Value R/O 0 R/O 1 R/O 1 R/O 1 R/O 0 R/O 0 R/O 1 R/O 1
BIT NUMBER 7-0
NAME Part Number ID Value
TYPE R/O
DEFAULT VALUE 0x73
DESCRIPTION Part Number ID Value: This READ-ONLY register contains a unique value that represents the XRT75L03D.
63
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER TABLE 22: CHIP REVISION NUMBER REGISTER - CR63 (ADDRESS LOCATION = 0X3F)
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1
ac
XRT75L03D
REV. 1.0.0
BIT 0
Chip Revision Number Value R/O 0 R/O 0 R/O 0 R/O 0 R/O X R/O X R/O X R/O X
BIT NUMBER 7-0
NAME Chip Revision Number Value
TYPE R/O
DEFAULT VALUE 0x0#
DESCRIPTION Chip Revision Number Value: This READ-ONLY register contains a value that represents the current revision of this XRT75L03D. This revision number will always be in the form of "0x0#", where "#" is a hexadecimal value that specifies the current revision of the chip. For example, the very first revision of this chip will contain the value "0x01".
THE PER-CHANNEL REGISTERS The XRT75L03D consists of 21 per-Channel Registers. Table 23 presents the overall Register Map with the Per-Channel Registers shaded. TABLE 23: COMMAND REGISTER ADDRESS MAP, WITHIN THE XRT75L03D 3-CHANNEL DS3/E3/STS-1 LIU W/ JITTER ATTENUATOR IC
ADDRESS 0x00 COMMAND REGISTER CR0 TYPE R/W REGISTER NAME APS/Redundancy Control Register
CHANNEL 0 CONTROL REGISTERS 0x01 0x02 0x03 0x04 0x05 0x06 0x07 CR1 CR2 CR3 CR4 CR5 CR6 CR7 R/O R/W R/O R/W R/W R/W R/W Source Level Interrupt Enable Register - Channel 0 Source Level Interrupt Status Register Channel 0 Alarm Status Register - Channel 0 Transmit Control Register - Channel 0 Receive Control Register - Channel 0 Channel Control Register - Channel 0 Jitter Attenuator Control Register - Channel 0
CHANNEL 1 CONTROL REGISTERS 0x08 0x09 0x0A 0x0B 0x0C CR8 CR9 CR10 CR11 CR12 R/O R/W RUR R/O R/W Reserved Source Level Interrupt Enable Register - Channel 1 Source Level Interrupt Status Register - Channel 1 Alarm Status Register - Channel 1 Transmit Control Register - Channel 1
64
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THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
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TABLE 23: COMMAND REGISTER ADDRESS MAP, WITHIN THE XRT75L03D 3-CHANNEL DS3/E3/STS-1 LIU W/ JITTER ATTENUATOR IC
ADDRESS 0x0D 0x0E 0x0F COMMAND REGISTER CR13 CR14 CR15 TYPE R/W R/W R/W REGISTER NAME Receive Control Register - Channel 1 Channel Control Register - Channel 1 Jitter Attenuator Control Register - Channel 1
CHANNEL 2 CONTROL REGISTERS 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 - 0x1F CR16 CR17 CR18 CR19 CR20 CR21 CR22 CR23 Reserved BLOCK LEVEL INTERRUPT ENABLE/STATUS REGISTERS (CHANNELS 0 - 2) 0x20 0x21 0x22 - 0x3D CR32 CR33 Reserved R/W R/O Block Level Interrupt Enable Register Block Level Interrupt Status Register Reserved DEVICE IDENTIFICATION REGISTERS 0x3E 0x3F CR62 CR63 R/O R/O Device Part Number Register Chip Revision Number Register R/W R/W RUR R/O R/W R/W R/W R/W Reserved Source Level Interrupt Enable Register - Channel 2 Source Level Interrupt Status Register - Channel 2 Alarm Status Register - Channel 2 Transmit Control Register - Channel 2 Receive Control Register - Channel 2 Channel Control Register - Channel 2 Jitter Attenuator Control Register - Channel 2
65
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REGISTER DESCRIPTION - PER CHANNEL REGISTERS
ac
XRT75L03D
REV. 1.0.0
TABLE 24: SOURCE LEVEL INTERRUPT ENABLE REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X01 Channel 1 Address Location = 0x09 Channel 2 Address Location = 0x11)
BIT 7 BIT 6 Unused BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Change of FL Change of LOL Change of LOS Change of Condition Condition Condition DMO Condition Interrupt Enable Interrupt Enable Interrupt Enable Interrupt Enable Ch 0 Ch 0 Ch 0 Ch 0 R/O 0 R/O 0 R/W 0 R/W 0 R/W 0 R/W 0
R/O 0
R/O 0
BIT NUMBER 7-4 3
NAME Reserved Change of FL Condition Interrupt Enable - Ch 0
TYPE R/O R/W
DEFAULT VALUE 0 0
DESCRIPTION
Change of FL (FIFO Limit Alarm) Condition Interrupt Enable - Ch 0: This READ/WRITE bit-field is used to either enable or disable the Change of FL Condition Interrupt. If the user enables this interrupt, then the XRT75L03D will generate an interrupt any time any of the following events occur.
* Whenever the Jitter Attenuator (within Channel 0)
declares the FL (FIFO Limit Alarm) condition.
* Whenever the Jitter Attenuator (within Channel 0) clears
the FL (FIFO Limit Alarm) condition. 0 - Disables the Change in FL Condition Interrupt. 1 - Enables the Change in FL Condition Interrupt. 2 Change of LOL Condition Interrupt Enable R/W 0 Change of Receive LOL (Loss of Lock) Condition Interrupt Enable - Channel 0: This READ/WRITE bit-field is used to either enable or disable the Change of Receive LOL Condition Interrupt. If the user enables this interrupt, then the XRT75L03D will generate an interrupt any time any of the following events occur.
* Whenever the Receive Section (within Channel 0)
declares the Loss of Lock Condition.
* Whenever the Receive Section (within Channel 0) clears
the Loss of Lock Condition. 0 - Disables the Change in Receive LOL Condition Interrupt. 1 - Enables the Change in Receive LOL Condition Interrupt.
66
XRT75L03D
REV. 1.0.0
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
NAME Change of LOS Condition Interrupt Enable TYPE R/W DEFAULT VALUE 0 DESCRIPTION Change of the Receive LOS (Loss of Signal) Defect Condition Interrupt Enable - Ch 0: This READ/WRITE bit-field is used to either enable or disable the Change of the Receive LOS Defect Condition Interrupt. If the user enables this interrupt, then the XRT75L03D will generate an interrupt any time any of the following events occur.
ac
BIT NUMBER 1
* Whenever the Receive Section (within Channel 0)
declares the LOS Defect Condition.
* Whenever the Receive Section (within Channel 0) clears
the LOS Defect condition. 0 - Disables the Change in the LOS Defect Condition Interrupt. 1 - Enables the Change in the LOS Defect Condition Interrupt. 0 Change of DMO Condition Interrupt Enable R/W 0 Change of Transmit DMO (Drive Monitor Output) Condition Interrupt Enable - Ch 0: This READ/WRITE bit-field is used to either enable or disable the Change of Transmit DMO Condition Interrupt. If the user enables this interrupt, then the XRT75L03D will generate an interrupt any time any of the following events occur.
* Whenever the Transmit Section toggles the DMO output
pin (or bit-field) to "1".
* Whenever the Transmit Section toggles the DMO output
pin (or bit-field) to "0". 0 - Disables the Change in the DMO Condition Interrupt. 1 - Enables the Change in the DMO Condition Interrupt.
67
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
ac
XRT75L03D
REV. 1.0.0
TABLE 25: SOURCE LEVEL INTERRUPT STATUS REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X02 Channel 1 Address Location = 0x0A Channel 2 Address Location = 0x12
BIT 7 BIT 6 Unused BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Change of FL Change of LOL Change of LOS Change of DMO Condition Condition Condition Condition Interrupt Status Interrupt Status nterrupt Status Interrupt Status Ch_n Ch_n Ch_n Ch_n R/O 0 R/O 0 RUR 0 RUR 0 RUR 0 RUR 0
R/O 0
R/O 0
BIT NUMBER 7-4 3
NAME Unused Change of FL Condition Interrupt Status
TYPE R/O RUR
DEFAULT VALUE 0 0
DESCRIPTION
Change of FL (FIFO Limit Alarm) Condition Interrupt Status - Ch 0: This RESET-upon-READ bit-field indicates whether or not the Change of FL Condition Interrupt (for Channel 0) has occurred since the last read of this register. 0 - Indicates that the Change of FL Condition Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the Change of FL Condition Interrupt has occurred since the last read of this register.
NOTE: The user can determine the current state of the FIFO Alarm condition by reading out the contents of Bit 3 (FL Alarm Declared) within the Alarm Status Register.
2 Change of LOL Condition Interrupt Status RUR 0 Change of Receive LOL (Loss of Lock) Condition Interrupt Status - Ch 0: This RESET-upon-READ bit-field indicates whether or not the Change of Receive LOL Condition Interrupt (for Channel 0) has occurred since the last read of this register. 0 - Indicates that the Change of Receive LOL Condition Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the Change of Receive LOL Condition Interrupt has occurred since the last read of this register.
NOTE: The user can determine the current state of the Receive LOL Defect condition by reading out the contents of Bit 2 (Receive LOL Defect Declared) within the Alarm Status Register.
68
XRT75L03D
REV. 1.0.0
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
NAME Change of LOS Condition Interrupt Status TYPE RUR DEFAULT VALUE 0 DESCRIPTION
ac
BIT NUMBER 1
Change of Receive LOS (Loss of Signal) Defect Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the Change of the Receive LOS Defect Condition Interrupt (for Channel 0) has occurred since the last read of this register. 0 - Indicates that the Change of the Receive LOS Defect Condition Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the Change of the Receive LOS Defect Condition Interrupt has occurred since the last read of this register.
NOTE: The user can determine the current state of the Receive LOS Defect condition by reading out the contents of Bit 1 (Receive LOS Defect Declared) within the Alarm Status Register.
0 Change of DMO Condition Interrupt Status RUR 0 Change of Transmit DMO (Drive Monitor Output) Condition Interrupt Status - Ch 0: This RESET-upon-READ bit-field indicates whether or not the Change of the Transmit DMO Condition Interrupt (for Channel 0) has occurred since the last read of this register. 0 - Indicates that the Change of the Transmit DMO Condition Interrupt has NOT occurred since the last read of this register. 1 - Indicates that the Change of the Transmit DMO Condition Interrupt has occurred since the last read of this register.
NOTE: The user can determine the current state of the Transmit DMO Condition by reading out the contents of Bit 0 (Transmit DMO Condition) within the Alarm Status Register.
69
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER TABLE 26: ALARM STATUS REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X03 Channel 1 Address Location = 0x0B Channel 2 Address Location = 0x13
BIT 7 Unused BIT 6 Loss of PRBS Pattern Sync BIT 5 Digital LOS Defect Declared BIT 4 Analog LOS Defect Declared BIT 3 FL (FIFO Limit) Alarm Declared R/O 0 BIT 2 BIT 1
ac
XRT75L03D
REV. 1.0.0
BIT 0 Transmit DMO Condition
Receive LOL Receive LOS Defect Defect Declared Declared
R/O 0
R/O 0
R/O 0
R/O 0
R/O 0
R/O 0
R/O 0
BIT NUMBER 7 6
NAME Unused Loss of PRBS Pattern Lock
TYPE R/O R/O
DEFAULT VALUE 0 0
DESCRIPTION
Loss of PRBS Pattern Lock Indicator: This READ-ONLY bit-field indicates whether or not the PRBS Receiver (within the Receive Section of Channel 0) is declaring PRBS Lock within the incoming PRBS pattern. If the PRBS Receiver detects a very large number of biterrors within its incoming data-stream, then it will declare the Loss of PRBS Lock Condition. Conversely, if the PRBS Receiver were to detect its predetermined PRBS pattern with the incoming DS3, E3 or STS-1 data-stream, (with little or no bit errors) then the PRBS Receiver will clear the Loss of PRBS Lock condition. 0 - Indicates that the PRBS Receiver is currently declaring the PRBS Lock condition within the incoming DS3, E3 or STS-1 data-stream. 1 - Indicates that the PRBS Receiver is currently declaring the Loss of PRBS Lock condition within the incoming DS3, E3 or STs-1 data-stream.
NOTE: This register bit is only valid if all of the following are true.
a. The PRBS Generator block (within the Transmit Section of the Chip is enabled). b. The PRBS Receiver is enabled. c. The PRBS Pattern (that is generated by the PRBS Generator) is somehow looped back into the Receive Path (via the Line-Side) and in-turn routed to the receive input of the PRBS Receiver.
70
XRT75L03D
REV. 1.0.0
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
NAME Digital LOS Defect Declared TYPE R/O DEFAULT VALUE 0 DESCRIPTION
ac
BIT NUMBER 5
Digital LOS Defect Declared: This READ-ONLY bit-field indicates whether or not the Digital LOS (Loss of Signal) detector is declaring the LOS Defect condition. For DS3 and STS-1 applications, the Digital LOS Detector will declare the LOS Defect condition whenever it detects an absence of pulses (within the incoming DS3 or STS-1 data-stream) for 160 consecutive bit-periods. Further, (again for DS3 and STS-1 applications) the Digital LOS Detector will clear the LOS Defect condition whenever it determines that the pulse density (within the incoming DS3 or STS-1 signal) is at least 33%. 0 - Indicates that the Digital LOS Detector is NOT declaring the LOS Defect Condition. 1 - Indicates that the Digital LOS Detector is currently declaring the LOS Defect condition.
NOTES: 1. LOS Detection (within each channel of the XRT75L03D) is performed by both an Analog LOS Detector and a Digital LOS Detector. The LOS state of a given Channel is simply a WIREDOR of the LOS Defect Declare states of these two detectors. 2. The current LOS Defect Condition (for the channel) can be determined by reading out the contents of Bit 1 (Receive LOS Defect Declared) within this register.
71
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
BIT NUMBER 4 NAME Analog LOS Defect Declared TYPE R/O DEFAULT VALUE 0 DESCRIPTION
ac
XRT75L03D
REV. 1.0.0
Analog LOS Defect Declared: This READ-ONLY bit-field indicates whether or not the Analog LOS (Loss of Signal) detector is declaring the LOS Defect condition. For DS3 and STS-1 applications, the Analog LOS Detector will declare the LOS Defect condition whenever it determines that the amplitude of the pulses (within the incoming DS3/STS-1 line signal) drops below a certain Analog LOS Defect Declaration threshold level. Conversely, (again for DS3 and STS-1 applications) the Analog LOS Detector will clear the LOS Defect condition whenever it determines that the amplitude of the pulses (within the incoming DS3/STS-1 line signal) has risen above a certain Analog LOS Defect Clearance threshold level. It should be noted that, in order to prevent "chattering" within the Analog LOS Detector output, there is some builtin hysteresis between the Analog LOS Defect Declaration and the Analog LOS Defect Clearance threshold levels. 0 - Indicates that the Analog LOS Detector is NOT declaring the LOS Defect Condition. 1 - Indicates that the Analog LOS Detector is currently declaring the LOS Defect condition.
NOTES: 1. LOS Detection (within each channel of the XRT75L03D) is performed by both an Analog LOS Detector and a Digital LOS Detector. The LOS state of a given Channel is simply a WIREDOR of the LOS Defect Declare states of these two detectors. 2. The current LOS Defect Condition (for the channel) can be determined by reading out the contents of Bit 1 (Receive LOS Defect Declared) within this register.
72
XRT75L03D
REV. 1.0.0
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
NAME FL Alarm Declared TYPE R/O DEFAULT VALUE 0 DESCRIPTION
ac
BIT NUMBER 3
FL (FIFO Limit) Alarm Declared: This READ-ONLY bit-field indicates whether or not the Jitter Attenuator block (within Channel_n) is currently declaring the FIFO Limit Alarm. The Jitter Attenuator block will declare the FIFO Limit Alarm anytime the Jitter Attenuator FIFO comes within two bit-periods of either overflowing or under-running. Conversely, the Jitter Attenuator block will clear the FIFO Limit Alarm anytime the Jitter Attenuator FIFO is NO longer within two bit-periods of either overflowing or underrunning. Typically, this Alarm will only be declared whenever there is a very serious problem with timing or jitter in the system. 0 - Indicates that the Jitter Attenuator block (within Channel_n) is NOT currently declaring the FIFO Limit Alarm condition. 1 - Indicates that the Jitter Attenuator block (within Channel_n) is currently declaring the FIFO Limit Alarm condition.
NOTE: This bit-field is only active if the Jitter Attenuator (within Channel_n) has been enabled.
2 Receive LOL Condition Declared R/O 0 Receive LOL (Loss of Lock) Condition Declared: This READ-ONLY bit-field indicates whether or not the Receive Section (within Channel_n) is currently declaring the LOL (Loss of Lock) condition. The Receive Section (of Channel_n) will declare the LOL Condition, if any one of the following conditions are met.
* If the frequency of the Recovered Clock signal differs
from that of the signal provided to the E3CLK input (for E3 applications), the DS3CLK input (for DS3 applications) or the STS-1CLK input (for STS-1 applications) by 0.5% (or 5000ppm) or more.
* If the frequency of the Recovered Clock signal differs
from the line-rate clock signal (for Channel_n) that has been generated by the SFM Clock Synthesizer PLL (for SFM Mode Operation) by 0.5% (or 5000ppm) or more. 0 - Indicates that the Receive Section of Channel_n is NOT currently declaring the LOL Condition. 1 - Indicates that the Receive Section of Channel_n is currently declaring the LOL Condition.
73
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
BIT NUMBER 1 NAME Receive LOS Defect Condition Declared TYPE R/O DEFAULT VALUE 0 DESCRIPTION
ac
XRT75L03D
REV. 1.0.0
Receive LOS (Loss of Signal) Defect Condition Declared: This READ-ONLY bit-field indicates whether or not the Receive Section (within Channel_n) is currently declaring the LOS defect condition. The Receive Section (of Channel_n) will declare the LOS defect condition, if any one of the following conditions is met.
* If the Digital LOS Detector declares the LOS defect
condition (for DS3 or STS-1 applications)
* If the Analog LOS Detector declares the LOS defect
condition (for DS3 or STS-1 applications)
* If the ITU-T G.775 LOS Detector declares the LOS
defect condition (for E3 applications). 0 - Indicates that the Receive Section of Channel_n is NOT currently declaring the LOS Defect Condition. 1 - Indicates that the Receive Section of Channel_n is currently declaring the LOS Defect condition. 0 Transmit DMO Condition Declared R/O 0 Transmit DMO (Drive Monitor Output) Condition Declared: This READ-ONLY bit-field indicates whether or not the Transmit Section of Channel_n is currently declaring the DMO Alarm condition. If configured accordingly, the Transmit Section will either internally or externally check the Transmit Output DS3/E3/ STS-1 Line signal for bipolar pulses via the TTIP_n and TRING_n output signals. If the Transmit Section were to detect no bipolar for 128 consecutive bit-periods, then it will declare the Transmit DMO Alarm condition. This particular alarm can be used to check for fault conditions on the Transmit Output Line Signal path. The Transmit Section will clear the Transmit DMO Alarm condition the instant that it detects some bipolar activity on the Transmit Output Line signal. 0 - Indicates that the Transmit Section of Channel_n is NOT currently declaring the Transmit DMO Alarm condition. 1 - Indicates that the Transmit Section of Channel_n is currently declaring the Transmit DMO Alarm condition.
74
XRT75L03D
REV. 1.0.0
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER TABLE 27: TRANSMIT CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X04 Channel 1 Address Location = 0x0C Channel 2 Address Location = 0x14
ac
BIT 7 Unused
BIT 6
BIT 5 Internal Transmit Drive Monitor
BIT 4 Insert PRBS Error
BIT 3 Unused
BIT 2 TAOS
BIT 1 TxCLKINV
BIT 0 TxLEV
R/O 0
R/O 0
R/W 0
R/W 0
R/O 0
R/W 0
R/W 0
R/W 0
BIT NUMBER 7-6 5
NAME Unused Internal Transmit Drive Monitor
TYPE R/O R/W
DEFAULT VALUE 0 0
DESCRIPTION
Internal Transmit Drive Monitor Enable - Channel_n: This READ/WRITE bit-field is used to configure the Transmit Section of Channel_n to either internally or externally monitor the TTIP_n and TRING_n output pins for bipolar pulses, in order to determine whether to declare the Transmit DMO Alarm condition. If the user configures the Transmit Section to externally monitor the TTIP_n and TRING_n output pins (for bipolar pulses) then the user must make sure that he/she has connected the MTIP_n and MRING_n input pins to their corresponding TTIP_n and TRING_n output pins (via a 274 ohm series resistor). If the user configures the Transmit Section to internally monitor the TTIP_n and TRING_n output pins (for bipolar pulses) then the user does NOT need to make sure that the MTIP_n and MRING_n input pins are connected to the TTIP_n and TRING_n output pins (via series resistors). This monitoring will be performed right at the TTIP_n and TRING_n output pads. 0 - Configures the Transmit Drive Monitor to externally monitor the TTIP_n and TRING_n output pins for bipolar pulses. 1 - Configures the Transmit Drive Monitor to internally monitor the TTIP_n and TRING_n output pins for bipolar pulses.
75
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
BIT NUMBER 4 NAME Insert PRBS Error TYPE R/W DEFAULT VALUE 0 DESCRIPTION
ac
XRT75L03D
REV. 1.0.0
Insert PRBS Error - Channel_n: A "0 to 1" transition within this bit-field configures the PRBS Generator (within the Transmit Section of Channel_n) to generate a single bit error within the outbound PRBS pattern-stream.
NOTES: 1. This bit-field is only active if the PRBS Generator and Receiver have been enabled within the corresponding Channel. 2. After writing the "1" into this register, the user must execute a write operation to clear this particular register bit to "0" in order to facilitate the next "0 to 1" transition in this bit-field.
3 2 Unused TAOS R/O R/W 0 0 Transmit All OneS Pattern - Channel_n: This READ/WRITE bit-field is used to command the Transmit Section of Channel_n to generate and transmit an unframed, All Ones pattern via the DS3, E3 or STS-1 line signal (to the remote terminal equipment). Whenever the user implements this configuration setting then the Transmit Section will ignore the data that it is accepting from the System-side equipment and overwrite this data with the "All Ones" Pattern. 0 - Configures the Transmit Section to transmit the data that it accepts from the System-side Interface. 1 - Configures the Transmit Section to generate and transmit the Unframed, All Ones pattern.
76
XRT75L03D
REV. 1.0.0
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
NAME TxCLKINV TYPE R/W DEFAULT VALUE 0 DESCRIPTION
ac
BIT NUMBER 1
Transmit Clock Invert Select - Channel_n: This READ/WRITE bit-field is used to select the edge of the TxCLK_n input that the Transmit Section of Channel_n will use to sample the TPDATA_n and TNDATA_n input pins, as described below. 0 - Configures the Transmit Section (within the corresponding channel) to sample the TPDATA_n and TNDATA_n input pins upon the falling edge of TxCLK_n. 1 - Configures the Transmit Section (within the corresponding channel) to sample the TPDATA_n and TNDATA_n input pins upon the rising edge of TxCLK_n.
NOTE:
Whenever this configuration setting is accomplished via the Host Mode, it is done on a per-channel basis.
0
TxLEV
R/W
0
Transmit Line Build-Out Select - Channel_n: This READ/WRITE bit-field is used to either enable or disable the Transmit Line Build-Out (e.g., pulse-shaping) circuit within the corresponding channel. The user should set this bit-field to either "0" or to "1" based upon the following guidelines. 0 - If the cable length between the Transmit Output (of the corresponding Channel) and the DSX-3/STSX-1 location is 225 feet or less. 1 - If the cable length between the Transmit Output (of the corresponding Channel) and the DSX-3/STSX-1 location is 225 feet or more. The user must follow these guidelines in order to insure that the Transmit Section (of Channel_n) will always generate a DS3 pulse that complies with the Isolated Pulse Template requirements per Bellcore GR-499-CORE, or an STS-1 pulse that complies with the Pulse Template requirements per Telcordia GR-253-CORE.
NOTE: This bit-field is ignored if the channel has been configured to operate in the E3 Mode.
77
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER TABLE 28: RECEIVE CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X05 Channel 1 Address Location = 0x0D Channel 2 Address Location = 0x15
BIT 7 Unused BIT 6 BIT 5 BIT 4 BIT 3 RxCLKINV BIT 2 LOSMUT Enable BIT 1 Receive Monitor Mode Enable R/W 0
ac
XRT75L03D
REV. 1.0.0
BIT 0 Receive Equalizer Enable R/W 0
Disable DLOS Disable ALOS Detector Detector
R/O 0
R/O 0
R/W 0
R/W 0
R/W 0
R/W 0
BIT NUMBER 7-6 5
NAME Unused Disable DLOS Detector
TYPE R/O R/W
DEFAULT VALUE 0 0
DESCRIPTION
Disable Digital LOS Detector - Channel_n: This READ/WRITE bit-field is used to either enable or disable the Digital LOS (Loss of Signal) Detector within Channel_n, as described below. 0 - Enables the Digital LOS Detector within Channel_n.
NOTE: This is the default condition.
1 - Disables the Digital LOS Detector within Channel_n.
NOTE: This bit-field is only active if Channel_n has been configured to operate in the DS3 or STS-1 Modes.
4 Disable ALOS Detector R/W 0 Disable Analog LOS Detector - Channel_n: This READ/WRITE bit-field is used to either enable or disable the Analog LOS (Loss of Signal) Detector within Channel_n, as described below. 0 - Enables the Analog LOS Detector within Channel_n.
NOTE: This is the default condition.
1 - Disables the Analog LOS Detector within Channel_n.
NOTE: This bit-field is only active if Channel_n has been configured to operate in the DS3 or STS-1 Modes.
3 RxCLKINV R/W 0 Receive Clock Invert Select - Channel_n: This READ/WRITE bit-field is used to select the edge of the RCLK_n output that the Receive Section of Channel_n will use to output the recovered data via the RPOS_n and RNEG_n output pins, as described below. 0 - Configures the Receive Section (within the corresponding channel) to output the recovered data via the RPOS_n and RNEG_n output pins upon the rising edge of RCLK_n. 1 - Configures the Receive Section (within the corresponding channel) to output the recovered data via the RPOS_n and RNEG_n output pins upon the falling edge of RCLK_n.
78
XRT75L03D
REV. 1.0.0
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
NAME LOSMUT Enable TYPE R/W DEFAULT VALUE 0 DESCRIPTION
ac
BIT NUMBER 2
Muting upon LOS Enable - Channel_n: This READ/WRITE bit-field is used to configure the Receive Section (within Channel_n) to automatically pull their corresponding Recovered Data Output pins (e.g., RPOS_n and RNEG_n) to GND anytime (and for the duration that) the Receive Section declares the LOS defect condition. In other words, this feature (if enabled) will cause the Receive Channel to automatically mute the Recovered data anytime (and for the duration that) the Receive Section declares the LOS defect condition. 0 - Disables the Muting upon LOS feature. In this setting the Receive Section will NOT automatically mute the Recovered Data whenever it is declaring the LOS defect condition. 1 - Enables the Muting upon LOS feature. In this setting the Receive Section will automatically mute the Recovered Data whenever it is declaring the LOS defect condition. Receive Monitor Mode Enable - Channel_n: This READ/WRITE bit-field is used to configure the Receive Section of Channel_n to operate in the Receive Monitor Mode. If the user configures the Receive Section to operate in the Receive Monitor Mode, then it will be able to receive a nominal DSX-3/STSX-1 signal that has been attenuator by 20dB of flat loss along with 6dB of cable loss, in an errorfree manner, and without declaring the LOS defect condition. 0 - Configures the corresponding channel to operate in the Normal Mode. 1 - Configure the corresponding channel to operate in the Receive Monitor Mode. Receive Equalizer Enable - Channel_n: This READ/WRITE register bit is used to either enable or disable the Receive Equalizer block within the Receive Section of Channel_n, as listed below. 0 - Disables the Receive Equalizer within the corresponding channel. 1 - Enables the Receive Equalizer within the corresponding channel.
1
Receive Monitor Mode Enable
R/W
0
0
Receive Equalizer Enable
R/W
0
NOTE: For virtually all applications, we recommend that the user set this bit-field to "1" (for all three channels) and enable the Receive Equalizer.
79
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER TABLE 29: CHANNEL CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X06 Channel 1 Address Location = 0x0E Channel 2 Address Location = 0x16
BIT 7 Unused BIT 6 BIT 5 PRBS Enable Ch_n R/O 0 R/W 0 BIT 4 RLB_n BIT 3 LLB_n BIT 2 E3_n BIT 1 STS-1/DS3_n
ac
XRT75L03D
REV. 1.0.0
BIT 0 SR/DR_n
R/O 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
BIT NUMBER 7-6 5
NAME Unused PRBS Enable
TYPE R/O R/W
DEFAULT VALUE 0 0
DESCRIPTION
PRBS Generator and Receiver Enable - Channel_n: This READ/WRITE bit-field is used to either enable or disable the PRBS Generator and Receiver within a given Channel of the XRT75L03D. If the user enables the PRBS Generator and Receiver, then the following will happen. 1. The PRBS Generator (which resides within the Transmit Section of the Channel) will begin to generate an unframed, 2^15-1 PRBS Pattern (for DS3 and STS-1 applications) and an unframed, 2^23-1 PRBS Pattern (for E3 applications). 2. The PRBS Receiver (which resides within the Receive Section of the Channel) will now be enabled and will begin to search the incoming data for the above-mentioned PRBS patterns. 0 - Disables both the PRBS Generator and PRBS Receiver within the corresponding channel. 1 - Enables both the PRBS Generator and PRBS Receiver within the corresponding channel.
NOTES: 1. To check and monitor PRBS Bit Errors, Bit 0 (SR/ DR_n) within this register Must be set to "0". This step will configure the RNEG_n/LCV_n output pin to function as the PRBS Error Indicator. In this case, external glue logic will be needed to monitor and count the number of PRBS Bit Errors that are detected by the PRBS Receiver. 2. If the user enables the PRBS Generator and PRBS Receiver, then the Channel will ignore the data that is being accepted from the System-side Equipment (via the TPDATA_n and TNDATA_n input pins) and will overwrite this outbound data with the PRBS Pattern. 3. Use of the PRBS Generator and Receiver is only available through the Host Mode.
80
XRT75L03D
REV. 1.0.0
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
NAME RLB_n TYPE R/W DEFAULT VALUE 0 DESCRIPTION Loop-Back Select - RLB Bit - Channel_n: This READ/WRITE bit-field along with the corresponding LLB_n bit-field is used to configure a given channel (within the XRT75L03D) into various loop-back modes. The relationship between the settings for this input pin, the corresponding LLB_n bit-field and the resulting Loop-back Mode is presented below.
ac
BIT NUMBER 4
LLB_n
RLB_n
L o o p -b a c k M o d e
0 0 1 1
0 1 0 1
N orm al (N o Loop-back) M ode R em ote Lo op-back M ode A nalog Lo cal Loop-back M ode D igital Loc al Loop-back M ode
3
LLB_n
R/W
0
Loop-Back Select - LLB Bit-field - Channel_n: Please see the description (above) for RLB_n. E3 Mode Select - Channel_n: This READ/WRITE bit-field, along with Bit 1 (STS-1/ DS3_n) within this particular register, is used to configure a given channel (of the XRT75L03D) into either the DS3, E3 or STS-1 Modes, as depicted below. 0 - Configures Channel_n to operate in either the DS3 or STS-1 Modes, depending upon the state of Bit 1 (STS-1/ DS3_n) within this same register. 1- Configures Channel_n to operate in the E3 Mode.
2
E3_n
R/W
0
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BIT NUMBER 1 NAME STS-1/DS3_n TYPE R/W DEFAULT VALUE 0 DESCRIPTION
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STS-1/DS3 Mode Select - Channel_n: This READ/WRITE bit-field, along with Bit 2 (E3_n) is used to configure a given channel (within the XRT75L03D) into either the DS3, E3 or STS-1 Modes. 0 - Configures Channel_n to operate in the DS3 Mode (provided by Bit 2 [E3_n], within this same register) has been set to "0"). 1 - Configures Channel_n to operate in the STS-1 Mode (provided that Bit 2 [E3_n], within the same register) has been set to "0".
NOTE: This bit-field is ignored if Bit 2 (E3_n) has been set to "1". In this case, Channel_n will be configured to operate in the E3 Mode.
0 SR/DR_n R/W 0 Single-Rail/Dual-Rail Select - Channel_n: This READ/WRITE bit-field is used to configure Channel_n to operate in either the Single-Rail or Dual-Rail Mode. If the user configures the Channel to operate in the SingleRail Mode, then all of the following will happen.
* The B3ZS/HDB3 Encoder and Decoder blocks (within
Channel_n) will be enabled.
* The Transmit Section of Channel_n will accept all of the
outbound data (from the System-side Equipment) via the TPDATA_n (or TxDATA_n) input pin.
* The Receive Section of each channel will output all of
the recovered data (to the System-side Equipment) via the RPOS_n output pin.
* The corresponding RNEG_n/LCV_n output pin will now
function as the LCV (Line Code Violation or Excessive Zero Event) indicator output pin for Channel_n. If the user configures Channel_n to operate in the DualRail Mode, then all of the following will happen.
* The B3ZS/HDB3 Encoder and Decoder blocks of
Channel_n will be disabled.
* The Transmit Section of Channel_n will be configured to
accept positive-polarity data via the TPDATA_n input pin and negative-polarity data via the TNDATA_n input pin.
* The Receive Section of Channel_n will pulse the
RPOS_n output pin "High" (for one period of RCLK_n) for each time a positive-polarity pulse is received via the RTIP_n/RRING_n input pins. Likewise, the Receive Section of each channel will also pulse the RNEG_n output pin "High" (for one period of RCLK_n) for each time a negative-polarity pulse is received via the RTIP_n/RRING_n input pins. 0 - Configures Channel_n to operate in the Dual-Rail Mode. 1 - Configures Channel_n to operate in the Single-Rail Mode.
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THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER TABLE 30: JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07 Channel 1 Address Location = 0x0F Channel 2 Address Location = 0x17
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BIT 7
BIT 6 Unused
BIT 5
BIT 4 SONET APS Recovery Time Disable Ch_n
BIT 3 JA RESET Ch_n
BIT 2 JA1 Ch_n
BIT 1 JA in Tx Path Ch_n
BIT 0 JA0 Ch_n
R/O 0
R/O 0
R/O 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
BIT NUMBER 7-3 4
NAME Unused SONET APS Recovery Time Mode Disable Ch_n
TYPE R/O R/W
DEFAULT VALUE 0 O
DESCRIPTION
SONET APS Recovery Time Mode Disable - Channel n: This READ/WRITE bit-field is used to either enable or disable the "SONET APS Recovery Time" Mode within the Jitter Attenuator, associated with Channel n. If this feature is enabled the Jitter Attenuator (associated with Channel n) will be configured such that the user's system will be able to comply with the APS Recovery Time requirements of 50ms (per Telcordia GR-253-CORE). If this feature is disabled the System using the XRT75L03D will NOT comply with the APS Recovery Time requirements of 50ms.
NOTE: In this case, "APS Recovery Time" is defined as the amount of time that will elapse between (a) the instant that Automatic Protection Switching (APS) is employed (either "automatically" or upon Software Command), and (b) the instant that an entity (which is responsible for acquiring and maintaining DS3/E3 frame synchronization with the DS3/E3 data-stream that has been de-mapped from SONET by the Mapper device) has reacquired DS3/E3 frame synchronization, after the APS event.
0 - Enables the "SONET APS Recovery Time" Mode. 1 - Disables the "SONET APS Recovery Time" Mode.
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BIT NUMBER 3 NAME JA RESET Ch_n TYPE R/W DEFAULT VALUE 0 DESCRIPTION
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Jitter Attenuator RESET - Channel_n: Writing a "0 to 1" transition within this bit-field will configure the Jitter Attenuator (within Channel_n) to execute a RESET operation. Whenever the user executes a RESET operation, then all of the following will occur.
* The READ and WRITE pointers (within the Jitter
Attenuator FIFO) will be reset to their default values.
* The contents of the Jitter Attenuator FIFO will be
flushed.
NOTE: The user must follow up any "0 to 1" transition with the appropriate write operate to set this bit-field back to "0", in order to resume normal operation with the Jitter Attenuator.
2 JA1 Ch_n R/W 0 Jitter Attenuator Configuration Select Input - Bit 1: This READ/WRITE bit-field, along with Bit 0 (JA0 Ch_n) is used to do any of the following.
* To enable or disable the Jitter Attenuator corresponding
to Channel_n.
* To select the FIFO Depth for the Jitter Attenuator within
Channel_n. The relationship between the settings of these two bitfields and the Enable/Disable States, and FIFO Depths is presented below.
JA0 0 0 1 1
JA1 0 1 0 1
Jitter Attenuator Mode FIFO Depth = 16 bits FIFO Depth = 32 bits SONET/SDH De-Sync Mode Jitter Attenuator Disabled
1
JA in Tx Path Ch_n
R/W
0
Jitter Attenuator in Transmit/Receive Path Select Bit: This input pin is used to configure the Jitter Attenuator (within Channel_n) to operate in either the Transmit or Receive path, as described below. 0 - Configures the Jitter Attenuator (within Channel_n) to operate in the Receive Path. 1 - Configures the Jitter Attenuator (within Channel_n) to operate in the Transmit Path. Jitter Attenuator Configuration Select Input - Bit 0: Please see the description for Bit 2 (JA1 Ch_n).
0
JA0 Ch_n
R/W
0
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8.0 DIAGNOSTIC FEATURES: 8.1
PRBS Generator and Detector:
The XRT75L03D contains an on-chip Pseudo Random Binary Sequence (PRBS) generator and detector for diagnostic purpose. This feature is only available in Host mode. With the PRBSEN_n bit = "1", the transmitter will send out PRBS of 223-1 in E3 rate or 215-1 in STS-1/DS3 rate. At the same time, the receiver PRBS detector is also enabled. When the correct PRBS pattern is detected by the receiver, the RNEG/LCV pin will go "Low" to indicate PRBS synchronization has been achieved. When the PRBS detector is not in sync the PRBSLS bit will be set to "1" and RNEG/LCV pin will go "High". With the PRBS mode enabled, the user can also insert a single bit error by toggling "INSPRBS" bit. This is done by writing a "1" to INSPRBS bit. The receiver at RNEG/LCV pin will pulse "High" for one RxClk cycle for every bit error detected. Any subsequent single bit error insertion must be done by first writing a "0" to INSPRBS bit and followed by a "1". Figure 25 shows the status of RNEG/LCV pin when the XRT75L03D is configured in PRBS mode.
NOTE: In PRBS mode, the device is forced to operate in Single-Rail Mode.
FIGURE 25. PRBS MODE
RClk
SYNC LOSS
RNEG/LCV
PRBS SYNC Single Bit Error
8.2
LOOPBACKS:
The XRT75L03D offers three loopback modes for diagnostic purposes. In Hardware mode, the loopback modes are selected via the RLB_n and LLB_n pins. In Host mode, the RLB_n and LLB_n bits n the Channel control registers select the loopback modes. 8.2.1 ANALOG LOOPBACK: In this mode, the transmitter outputs (TTIP_n and TRING_n) are connected internally to the receiver inputs (RTIP_n and RRING_n) as shown in Figure 26. Data and clock are output at RCLK_n, RPOS_n and RNEG_n pins for the corresponding transceiver. Analog loopback exercises most of the functional blocks of the device including the jitter attenuator which can be selected in either the transmit or receive path. XRT75L03D can be configured in Analog Loopback either in Hardware mode via the LLB_n and RLB_n pins or in Host mode via LLB_n and RLB_n bits in the channel control registers.
NOTES: 1. In the Analog loopback mode, data is also output via TTIP_n and TRING_n pins. 2. Signals on the RTIP_n and RRING_n pins are ignored during analog loopback.
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TCLK TPDATA TNDATA
1 HDB3/B3ZS ENCODER
JITTER 2 ATTENUATOR
TIMING CONTROL
TTIP Tx TRING
RCLK RPOS RNEG
1
JITTER 2 ATTENUATOR
1 HDB3/B3ZS DECODER
DATA & CLOCK RECOVERY
RTIP Rx RRING
if enabled 2 if enabled and selected in either Receive or Transmit path
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THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER DIGITAL LOOPBACK:
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8.2.2
The Digital Loopback function is available either in Hardware mode or Host mode. When the Digital Loopback is selected, the transmit clock (TxClk_n) and transmit data inputs (TPDATA_n & TNDATA_n) are looped back and output onto the RxClk_n, RPOS_n and RNEG_n pins as shown in Figure 27. FIGURE 27. DIGITAL LOOPBACK
TCLK TPDATA TNDATA
1 HDB3/B3ZS ENCODER
JITTER 2 ATTENUATOR
TIMING CONTROL
TTIP Tx TRING
RCLK RPOS RNEG
1 2
JITTER 2 ATTENUATOR
1 HDB3/B3ZS DECODER
DATA & CLOCK RECOVERY
RTIP Rx RRING
if enabled if enabled and selected in either Receive or Transmit path
8.2.3
REMOTE LOOPBACK:
With Remote loopback activated as shown in Figure 28, the receive data on RTIP and RRING is looped back after the jitter attenuator (if selected in receive or transmit path) to the transmit path using RxClk as transmit timing. The receive data is also output via the RPOS and RNEG pins. During the remote loopback mode, if the jitter attenuator is selected in the transmit path, the receive data after the Clock and Data Recovery Block is looped back to the transmit path and passed through the jitter attenuator using RxClk as the transmit timing.
NOTE: Input signals on TxClk, TPDATA and TNDATA are ignored during Remote loopback.
FIGURE 28. REMOTE LOOPBACK
TCLK TPDATA TNDATA
1 HDB3/B3ZS ENCODER
JITTER 2 ATTENUATOR
TIMING CONTROL
TTIP Tx TRING
RCLK RPOS RNEG HDB3/B3ZS DECODER
1
JITTER 2 ATTENUATOR
DATA & CLOCK RECOVERY
RTIP Rx RRING
1 if enabled 2 if enabled and selected in either Receive or Transmit path
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TRANSMIT ALL ONES (TAOS):
Transmit All Ones (TAOS) can be set either in Hardware mode by pulling the TAOS_n pins "High" or in Host mode by setting the TAOS_n control bits to "1" in the Channel control registers. When the TAOS is set, the Transmit Section generates and transmits a continuous AMI all "1's" pattern on TTIP_n and TRING_n pins. The frequency of this "1's" pattern is determined by TClk_n.TAOS data path is shown in Figure 29. TAOS does not operate in Analog loopback or Remote Digital loopback mode. It will function in Digital loopback mode. FIGURE 29. TRANSMIT ALL ONES (TAOS)
TCLK TPDATA TNDATA
1 HDB3/B3ZS ENCODER
JITTER 2 ATTENUATOR
TIMING CONTROL
Tx
TTIP Transmit All 1 TRING
TAOS
RCLK RPOS RNEG
1 2
1 HDB3/B3ZS DECODER
JITTER 2 ATTENUATOR
DATA & CLOCK RECOVERY
RTIP Rx RRING
if enabled if enabled and selected in either Receive or Transmit path
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9.0 THE SONET/SDH DE-SYNC FUNCTION WITHIN THE XRT75L03D The XRT75L03D LIU IC is very similar to the XRT75L03 in that they are both 3-Channel DS3/E3/STS-1 LIU devices that also contain Jitter Attenuator blocks within each of the three channels. They are also pin to pin compatible with each other. However, the Jitter Attenuators within the XRT75L03D has some enhancements over and above those within the XRT75L03 (non-D) device. The Jitter Attenuator blocks within the XRT75L03D will support all of the modes and features that exist in the XRT75L03 (non-D) device and in addition they also support a SONET/SDH De-Sync Mode not available within the XRT75L03D.
NOTE: The "D" suffix within the part number, XRT75L03D stands for "De-Sync".
The SONET/SDH De-Sync feature of the Jitter Attenuator blocks in the XRT75L03D permits the user to design a SONET/SDH PTE (Path Terminating Equipment) that will comply with all of the following Intrinsic Jitter and Wander requirements.
* For SONET Applications
s s
Category I Intrinsic Jitter Requirements per Telcordia GR-253-CORE (for DS3 Applications) ANSI T1.105.03b-1997 - SONET Jitter at Network Interfaces - DS3 Wander Supplement Jitter and Wander Generation Requirements per ITU-T G.783 (for DS3 and E3 Applications)
* For SDH Applications
s
Specifically, if the user designs in the XRT75L03D along with a SONET/SDH Mapper IC (which can be realized as either a standard product or as a custom logic solution, in an ASIC or FPGA), then the followind can be accomplished;
* The Mapper can receive an STS-N or an STM-M signal (which is carrying asynchronously-mapped DS3 and/
or E3 signals) and byte de-interleave this data into N STS-1 or 3*M VC-3 signals
* The Mapper will then terminate these STS-1 or VC-3 signals and will de-map out this DS3 or E3 data from
the incoming STS-1 SPEs or VC-3s, and output this DS3 or E3 to the DS3/E3 Facility-side towards the XRT75L03D
* This DS3 or E3 signal (as it is output from these Mapper devices) will contain a large amount intrinsic jitter
and wander due to (1) the process of asynchronously mapping a DS3 or E3 signal into a SONET or SDH signal, (2) the occurrence of Pointer Adjustments within the SONET or SDH signal (transporting these DS3 or E3 signals) as it traverses the SONET/SDH network, and (3) clock gapping.
* When the XRT75L03D has been configured to operate in the "SONET/SDH De-Sync" Mode, then it will (1)
accept this jittery DS3 or E3 clock and data signal from the Mapper device (via the Transmit System-side interface) and (2) through the Jitter Attenuator, the XRT75L03D will reduce the Jitter and Wander amplitude within these DS3 or E3 signals such that they (when output onto the line) will comply with the abovementioned intrinsic jitter and wander specifications. 9.1
BACKGROUND AND DETAILED INFORMATION - SONET DE-SYNC APPLICATIONS
This section provides an in-depth discussion on the mechanisms that will cause Jitter and Wander within a DS3 or E3 signal that is being transported across a SONET or SDH Network. A lot of this material is introductory, and can be skipped by the engineer that is already experienced in SONET/SDH designs. In this case, the user should proceed directly to "Section 9.8, Designing with the XRT75L03D" on page 118, which describes how to configure the XRT75L03D in the appropriate set of modes in order to support this application. In the wide-area network (WAN) in North America it is often necessary to transport a DS3 signal over a long distance (perhaps over a thousand miles) in order to support a particular service. Now rather than realizing this transport of DS3 data, by using over a thousand miles of coaxial cable (interspaced by a large number of DS3 repeaters) a common thing to do is to route this DS3 signal to a piece of equipment (such as a Terminal MUX, which in the "SONET Community" is known as a PTE or Path Terminating Equipment). This Terminal MUX will asynchronously map the DS3 signal into a SONET signal. At this point, the SONET network will now transport this asynchronously mapped DS3 signal from one PTE to another PTE (which is located at the other end of the SONET network). Once this SONET signal arrives at the remote PTE, this DS3 signal will then be extracted from the SONET signal, and will be output to some other DS3 Terminal Equipment for further processing.
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Similar things are done outside of North America. In this case, this DS3 or E3 signal is routed to a PTE, where it is asynchronously mapped into an SDH signal. This asynchronously mapped DS3 or E3 signal is then transported across the SDH network (from one PTE to the PTE at the other end of the SDH network). Once this SDH signal arrives at the remote PTE, this DS3 or E3 signal will then be extracted from the SDH signal, and will be output to some other DS3/E3 Terminal Equipment for further processing. Figure 30 presents an illustration of this approach to transporting DS3 data over a SONET Network FIGURE 30. A SIMPLE ILLUSTRATION OF A DS3 SIGNAL BEING MAPPED INTO AND TRANSPORTED OVER THE SONET NETWORK
SONET Network
DS3 Data
PTE PTE
PTE PTE
DS3 Data
As mentioned above a DS3 or E3 signal will be asynchronously mapped into a SONET or SDH signal and then transported over the SONET or SDH network. At the remote PTE this DS3 or E3 signal will be extracted (or de-mapped) from this SONET or SDH signal, where it will then be routed to DS3 or E3 terminal equipment for further processing. In order to insure that this "de-mapped" DS3 or E3 signal can be routed to any industry-standard DS3 or E3 terminal equipment, without any complications or adverse effect on the network, the Telcordia and ITU-T standard committees have specified some limits on both the Intrinsic Jitter and Wander that may exist within these DS3 or E3 signals as they are de-mapped from SONET/SDH. As a consequence, all PTEs that maps and de-mapped DS3/E3 signals into/from SONET/SDH must be designed such that the DS3 or E3 data that is de-mapped from SONET/SDH by these PTEs must meet these Intrinsic Jitter and Wander requirements. As mentioned above, the XRT75L03D can assist the System Designer (of SONET/SDH PTE) by insuring that their design will meet these Intrinsic Jitter and Wander requirements. This section of the data sheet will present the following information to the user.
* Some background information on Mapping DS3/E3 signals into SONET/SDH and de-mapping DS3/E3
signals from SONET/SDH.
* A brief discussion on the causes of jitter and wander within a DS3 or E3 signal that mapped into a SONET/
SDH signal, and is transported across the SONET/SDH Network.
* A brief review of these Intrinsic Jitter and Wander requirements in both SONET and SDH applications. * A brief review on the Intrinsic Jitter and Wander measurement results (of a de-mapped DS3 or E3 signal)
whenever the XRT75L03D is used in a system design.
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* A detailed discussion on how to design with and configure the XRT75L03D such that the end-system will
meet these Intrinsic Jitter and Wander requirements. In a SONET system, the relevant specification requirements for Intrinsic Jitter and Wander (within a DS3 signal that is mapped into and then de-mapped from SONET) are listed below.
* Telcordia GR-253-CORE Category I Intrinsic Jitter Requirements for DS3 Applications (Section 5.6), and * ANSI T1.105.03b-1997 - SONET Jitter at Network Interfaces - DS3 Wander Supplement
In general, there are three (3) sources of Jitter and Wander within an asynchronously-mapped DS3 signal that the system designer must be aware of. These sources are listed below.
* Mapping/De-Mapping Jitter * Pointer Adjustments * Clock Gapping
Each of these sources of jitter/wander will be defined and discussed in considerable detail within this Section. In order to accomplish all of this, this particular section will discuss all of the following topics in details.
* How DS3 data is mapped into SONET, and how this mapping operation contributes to Jitter and Wander
within this "eventually de-mapped" DS3 signal.
* How this asynchronously-mapped DS3 data is transported throughout the SONET Network, and how
occurrences on the SONET network (such as pointer adjustments) will further contributes to Jitter and Wander within the "eventually de-mapped" DS3 signal.
* A review of the Category I Intrinsic Jitter Requirements (per Telcordia GR-253-CORE) for DS3 applications * A review of the DS3 Wander requirements per ANSI T1.105.03b-1997 * A review of the Intrinsic Jitter and Wander Capabilities of the XRT75L03D in a typical system application * An in-depth discussion on how to design with and configure the XRT75L03D to permit the system to the
meet the above-mentioned Intrinsic Jitter and Wander requirements
NOTE: An in-depth discussion on SDH De-Sync Applications will be presented in the next revision of this data sheet.
9.2
MAPPING/DE-MAPPING JITTER/WANDER
Mapping/De-Mapping Jitter (or Wander) is defined as that intrinsic jitter (or wander) that is induced into a DS3 signal by the "Asynchronous Mapping" process. This section will discuss all of the following aspects of Mapping/De-Mapping Jitter.
* How DS3 data is mapped into an STS-1 SPE * How frequency offsets within either the DS3 signal (being mapped into SONET) or within the STS-1 signal
itself contributes to intrinsic jitter/wander within the DS3 signal (being transported via the SONET network). 9.2.1 HOW DS3 DATA IS MAPPED INTO SONET Whenever a DS3 signal is asynchronously mapped into SONET, this mapping is typically accomplished by a PTE accepting DS3 data (from some remote terminal) and then loading this data into certain bit-fields within a given STS-1 SPE (or Synchronous Payload Envelope). At this point, this DS3 signal has now been asynchronously mapped into an STS-1 signal. In most applications, the SONET Network will then take this particular STS-1 signal and will map it into "higher-speed" SONET signals (e.g., STS-3, STS-12, STS-48, etc.) and will then transport this asynchronously mapped DS3 signal across the SONET network, in this manner. As this "asynchronously-mapped" DS3 signal approaches its "destination" PTE, this STS-1 signal will eventually be de-mapped from this STS-N signal. Finally, once this STS-1 signal reaches the "destination" PTE, then this asynchronously-mapped DS3 signal will be extracted from this STS-1 signal. 9.2.1.1
A Brief Description of an STS-1 Frame
In order to be able to describe how a DS3 signal is asynchronously mapped into an STS-1 SPE, it is important to define and understand all of the following.
* The STS-1 frame structure
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* The STS-1 SPE (Synchronous Payload Envelope) * Telcordia GR-253-CORE's recommendation on mapping DS3 data into an STS-1 SPE
An STS-1 frame is a data-structure that consists of 810 bytes (or 6480 bits). A given STS-1 frame can be viewed as being a 9 row by 90 byte column array (making up the 810 bytes). The frame-repetition rate (for an STS-1 frame) is 8000 frames/second. Therefore, the bit-rate for an STS-1 signal is (6480 bits/frame * 8000 frames/sec =) 51.84Mbps. A simple illustration of this SONET STS-1 frame is presented below in Figure 31. FIGURE 31. A SIMPLE ILLUSTRATION OF THE SONET STS-1 FRAME
90 Bytes
9 Rows
STS-1 Frame (810 Bytes)
Last Byte of the STS-1 Frame First Byte of the STS-1 Frame
Figure 31 indicates that the very first byte of a given STS-1 frame (to be transmitted or received) is located in the extreme upper left hand corner of the 90 column by 9 row array, and that the very last byte of a given STS1 frame is located in the extreme lower right-hand corner of the frame structure. Whenever a Network Element transmits a SONET STS-1 frame, it starts by transmitting all of the data, residing within the top row of the STS1 frame structure (beginning with the left-most byte, and then transmitting the very next byte, to the right). After the Network Equipment has completed its transmission of the top or first row, it will then proceed to transmit the second row of data (again starting with the left-most byte, first). Once the Network Equipment has transmitted the last byte of a given STS-1 frame, it will proceed to start transmitting the very next STS-1 frame. The illustration of the STS-1 frame (in Figure 31) is very simplistic, for multiple reasons. One major reason is that the STS-1 frame consists of numerous types of bytes. For the sake of discussion within this data sheet, the STS-1 frame will be described as consisting of the following types (or groups) of bytes.
* The Transport Overheads (or TOH) Bytes * The Envelope Capacity Bytes
9.2.1.1.1 The Transport Overhead (TOH) Bytes The Transport Overhead or TOH bytes occupy the very first three (3) byte columns within each STS-1 frame. Figure 32 presents another simple illustration of an STS-1 frame structure. However, in this case, both the TOH and the Envelope Capacity bytes are designated in this Figure.
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FIGURE 32. A SIMPLE ILLUSTRATION OF THE STS-1 FRAME STRUCTURE WITH THE TOH AND THE ENVELOPE CAPACITY BYTES DESIGNATED
90 Bytes
3 Bytes
87 Bytes
TOH
Envelope Capacity
9 Row
Since the TOH bytes occupy the first three byte columns of each STS-1 frame, and since each STS-1 frame consists of nine (9) rows, then we can state that the TOH (within each STS-1 frame) consists of 3 byte columns x 9 rows = 27 bytes. The byte format of the TOH is presented below in Figure 33.
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3 Byte Columns
87 Byte Columns
A1 A1 B1 B1 D1 D1 H1 H1
9 Rows
A2 A2 E1 E1 D2 D2 H2 H2 K1 K1 D5 D5 D8 D8 D11 D11 M0 M0
C1 C1 F1 F1 D3 D3 H3 H3 K2 K2 D6 D6 D9 D9 D12 D12 E2 E2 The TOH Bytes
B2 B2 D4 D4 D7 D7 D10 D10 S1 S1
Envelope Capacity Envelope Capacity Bytes Bytes
In general, the role/purpose of the TOH bytes is to fulfill the following functions.
* To support STS-1 Frame Synchronization * To support Error Detection within the STS-1 frame * To support the transmission of various alarm conditions such as RDI-L (Line - Remote Defect Indicator) and
REI-L (Line - Remote Error Indicator)
* To support the Transmission and Reception of "Section Trace" Messages * To support the Transmission and Reception of OAM&P Messages via the DCC Bytes (Data Communication
Channel bytes - D1 through D12 byte) The roles of most of the TOH bytes is beyond the scope of this Data Sheet and will not be discussed any further. However, there are a three TOH bytes that are important from the stand-point of this data sheet, and will discussed in considerable detail throughout this document. These are the H1 and H2 (e.g., the SPE Pointer) bytes and the H3 (e.g., the Pointer Action) byte. Figure 34 presents an illustration of the Byte-Format of the TOH within an STS-1 Frame, with the H1, H2 and H3 bytes highlighted.
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FIGURE 34. THE BYTE-FORMAT OF THE TOH WITHIN AN STS-1 FRAME
3 Byte Columns
87 Byte Columns
A1 A1 B1 B1 D1 D1 H1 H1
9 Rows
A2 A2 E1 E1 D2 D2 H2 H2 K1 K1 D5 D5 D8 D8 D11 D11 M0 M0
C1 C1 F1 F1 D3 D3 H3 H3 K2 K2 D6 D6 D9 D9 D12 D12 E2 E2 The TOH Bytes
B2 B2 D4 D4 D7 D7 D10 D10 S1 S1
Envelope Capacity Envelope Capacity Bytes Bytes
Although the role of the H1, H2 and H3 bytes will be discussed in much greater detail in "Section 9.3, Jitter/ Wander due to Pointer Adjustments" on page 102. For now, we will simply state that the role of these bytes is two-fold.
* To permit a given PTE (Path Terminating Equipment) that is receiving an STS-1 data to be able to locate the
STS-1 SPE (Synchronous Payload Envelope) within the Envelope Capacity of this incoming STS-1 data stream and,
* To inform a given PTE whenever Pointer Adjustment and NDF (New Data Flag) events occur within the
incoming STS-1 data-stream. 9.2.1.1.2 The Envelope Capacity Bytes within an STS-1 Frame In general, the Envelope Capacity Bytes are any bytes (within an STS-1 frame) that exist outside of the TOH bytes. In short, the Envelope Capacity contains the STS-1 SPE (Synchronous Payload Envelope). In fact, every single byte that exists within the Envelope Capacity also exists within the STS-1 SPE. The only difference that exists between the "Envelope Capacity" as defined in Figure 33 and Figure 34 above and the STS-1 SPE is that the Envelope Capacity is aligned with the STS-1 framing boundaries and the TOH bytes; whereas the STS-1 SPE is NOT aligned with the STS-1 framing boundaries, nor the TOH bytes. The STS-1 SPE is an "87 byte column x 9 row" data-structure (which is the exact same size as is the Envelope Capacity) that is permitted to "float" within the "Envelope Capacity". As a consequence, the STS-1 SPE (within an STS-1 data-stream) will typically straddle across an STS-1 frame boundary. 9.2.1.1.3 The Byte Structure of the STS-1 SPE As mentioned above, the STS-1 SPE is an 87 byte column x 9 row structure. The very first column within the STS-1 SPE consists of some overhead bytes which are known as the "Path Overhead" (or POH) bytes. The remaining portions of the STS-1 SPE is available for "user" data. The Byte Structure of the STS-1 SPE is presented below in Figure 35.
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87 Bytes 1 Byte 86 Bytes
9 Rows
J1 B3 C2 G1 F2 H4 Z3 Z4 Z5
Payload (or User) Data
In general, the role/purpose of the POH bytes is to fulfill the following functions.
* To support error detection within the STS-1 SPE * To support the transmission of various alarm conditions such as RDI-P (Path - Remote Defect Indicator) and
REI-P (Path - Remote Error Indicator)
* To support the transmission and reception of "Path Trace" Messages
The role of the POH bytes is beyond the scope of this data sheet and will not be discussed any further. 9.2.1.2
Mapping DS3 data into an STS-1 SPE
Now that we have defined the STS-1 SPE, we can now describe how a DS3 signal is mapped into an STS-1 SPE. As mentioned above, the STS-1 SPE is basically an 87 byte column x 9 row structure of data. The very first byte column (e.g., in all 9 bytes) consists of the POH (Path Overhead) bytes. All of the remaining bytes within the STS-1 SPE is simply referred to as "user" or "payload" data because this is the portion of the STS-1 signal that is used to transport "user data" from one end of the SONET network to the other. Telcordia GR253-CORE specifies the approach that one must use to asynchronously map DS3 data into an STS-1 SPE. In short, this approach is presented below in Figure 36.
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FIGURE 36. AN ILLUSTRATION OF TELCORDIA GR-253-CORE'S RECOMMENDATION ON HOW MAP DS3 DATA INTO AN STS-1 SPE
*
For DS3 Mapping, the STS-1 SPE has the following structure.
87 bytes R R R R R R R R R R R R R R R R R R C1 C1 C1 C1 C1 C1 C1 C1 C1 25I 25I 25I 25I 25I 25I 25I 25I 25I R R R R R R R R R C2 C2 C2 C2 C2 C2 C2 C2 C2 I I I I I I I I I 25I 25I 25I 25I 25I 25I 25I 25I 25I
i = DS3 data
R R R R R R R R R
C3 C3 C3 C3 C3 C3 C3 C3 C3
I I I I I I I I I
25I 25I 25I 25I 25I 25I 25I 25I 25I
POH
I = [i, i, i, i, i, i, i, i] R = [r, r, r, r, r, r, r, r] C1 = [r, r, c, i, i, i, i, i] C2 = [c, c, r, r, r, r, r, r] C3 = [c, c, r, r, o, o, r, s]
Fixed Stuff
r = fixed stuff bit c = stuff control bit s = stuff opportunity bit o = overhead communications channel bit
Figure 36 was copied directly out of Telcordia GR-253-CORE. However, this figure can be simplified and redrawn as depicted below in Figure 37. FIGURE 37. A SIMPLIFIED "BIT-ORIENTED" VERSION OF TELCORDIA GR-253-CORE'S RECOMMENDATION ON HOW TO MAP DS3 DATA INTO AN STS-1 SPE
18r 18r 18r 18r 18r 18r 18r 18r 18r
c c c c c c c c c
205i 205i 205i 205i 205i 205i 205i 205i 205i
16r 16r 16r 16r 16r 16r 16r 16r 16r
2c 2c 2c 2c 2c 2c 2c 2c 2c
6r 6r 6r 6r 6r 6r 6r 6r 6r
208i 208i 208i 208i 208i 208i 208i 208i 208i
16r 16r 16r 16r 16r 16r 16r 16r 16r
2c 2c 2c 2c 2c 2c 2c 2c 2c
2r 2r 2r 2r 2r 2r 2r 2r 2r
2o 2o 2o 2o 2o 2o 2o 2o 2o
1r 1r 1r 1r 1r 1r 1r 1r 1r
s s s s s s s s s
208i 208i 208i 208i 208i 208i 208i 208i 208i
POH
r c i s
- Fixed Stuff Bits - Stuff Control/Indicator Bits - DS3 Data Bits - Stuff Opportunity Bits
o
- Overhead Communication Bits
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Figure 37 presents an alternative illustration of Telcordia GR-253-CORE's recommendation on how to asynchronously map DS3 data into an STS-1 SPE. In this case, the STS-1 SPE bit-format is expressed purely in the form of "bit-types" and "numbers of bits within each of these types of bits". If one studies this figure closely he/she will notice that this is the same "87 byte column x 9 row" structure that we have been talking about when defining the STS-1 SPE. However, in this figure, the "user-data" field is now defined and is said to consist of five (5) different types of bits. Each of these bit-types play a role when asynchronously mapping a DS3 signal into an STS-1 SPE. Each of these types of bits are listed and described below. Fixed Stuff Bits Fixed Stuff bits are simply "space-filler" bits that simply occupy space within the STS-1 SPE. These bit-fields have no functional role other than "space occupation". Telcordia GR-253-CORE does not define any particular value that these bits should be set to. Each of the 9 rows, within the STS-1 SPE will contain 59 of these "fixed stuff" bits. DS3 Data Bits The DS3 Data-Bits are (as its name implies) used to transport the DS3 data-bits within the STS-1 SPE. If the STS-1 SPE is transporting a framed DS3 data-stream, then these DS3 Data bits will carry both the "DS3 payload data" and the "DS3 overhead bits". Each of the 9 rows, within the STS-1 SPE will contain 621 of these "DS3 Data bits". This means that each STS-1 SPE contains 5,589 of these DS3 Data bit-fields. Stuff Opportunity Bits The "Stuff" Opportunity bits will function as either a "stuff" (or junk) bit, or it will carry a DS3 data-bit. The decision as to whether to have a "Stuff Opportunity" bit transport a "DS3 data-bit" or a "stuff" bit depends upon the "timing differences" between the DS3 data that is being mapped into the STS-1 SPE and the timing source that is driving the STS-1 circuitry within the PTE. As will be described later on, these "Stuff Opportunity" Bits play a very important role in "frequency-justifying" the DS3 data that is being mapped into the STS-1 SPE. These "Stuff Opportunity" bits also play a critical role in inducing Intrinsic Jitter and Wander within the DS3 signal (as it is de-mapped by the remote PTE). Each of the 9 rows, within the STS-1 SPE consists of one (1) Stuff Opportunity bit. Hence, there are a total of nine Stuff Opportunity" bits within each STS-1 SPE. Stuff Control/Indicator Bits Each of the nine (9) rows within the STS-1 SPE contains five (5) Stuff Control/Indicator bits. The purpose of these "Stuff Control/Indicator" bits is to indicate (to the de-mapping PTE) whether the "Stuff Opportunity" bits (that resides in the same row) is a "Stuff" bit or is carrying a DS3 data bit. If all five of these "Stuff Control/Indicator" bits, within a given row are set to "0", then this means that the corresponding "Stuff Opportunity" bit (e.g., the "Stuff Opportunity" bit within the same row) is carrying a DS3 data bit. Conversely, if all five of these "Stuff Control/Indicator" bits, within a given row are set to "1" then this means that the corresponding "Stuff Opportunity" bit is carrying a "stuff" bit. Overhead Communication Bits Telcordia GR-253-CORE permits the user to use these two bits (for each row) as some sort of "Communications" bit. Some Mapper devices, such as the XRT94L43 12-Channel DS3/E3/STS-1 to STS-12/ STM-1 Mapper and the XRT94L33 3-Channel DS3/E3/STS-1 to STS-3/STM-1 Mapper IC (both from Exar Corporation) do permit the user to have access to these bit-fields. However, in general, these particular bits can also be thought of as "Fixed Stuff" bits, that mostly have a "space occupation" function. 9.2.2 DS3 Frequency Offsets and the Use of the "Stuff Opportunity" Bits In order to fully convey the role that the "stuff-opportunity" bits play, when mapping DS3 data into SONET, we will present a detailed discussion of each of the following "Mapping DS3 into STS-1" scenarios.
* The Ideal Case (e.g., with no frequency offsets) * The 44.736Mbps + 1 ppm Case
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* The 44.736MHz - 1ppm Case
Throughout each of these cases, we will discuss how the resulting "bit-stuffing" (that was done when mapping the DS3 signal into SONET) affects the amount of intrinsic jitter and wander that will be present in the DS3 signal, once it is ultimately de-mapped from SONET. 9.2.2.1
The Ideal Case for Mapping DS3 data into an STS-1 Signal (e.g., with no Frequency Offsets)
Let us assume that we are mapping a DS3 signal, which has a bit rate of exactly 44.736Mbps (with no frequency offset) into SONET. Further, let us assume that the SONET circuitry within the PTE is clocked at exactly 51.84MHz (also with no frequency offset), as depicted below. FIGURE 38. A SIMPLE ILLUSTRATION OF A DS3 DATA-STREAM BEING MAPPED INTO AN STS-1 SPE, VIA A PTE
DS3_Data_In
STS-1_Data_Out
PTE PTE
44.736MHz + 0ppm 51.84MHz + 0ppm
Given the above-mentioned assumptions, we can state the following.
* The DS3 data-stream has a bit-rate of exactly 44.736Mbps * The PTE will create 8000 STS-1 SPE's per second * In order to properly map a DS3 data-stream into an STS-1 data-stream, then each STS-1 SPE must carry
(44.736Mbps/8000 =) 5592 DS3 data bits. Is there a Problem? According to Figure 37, each STS-1 SPE only contains 5589 bits that are specifically designated for "DS3 data bits". In this case, each STS-1 SPE appears to be three bits "short". No there is a Simple Solution No, earlier we mentioned that each STS-1 SPE consists of nine (9) "Stuff Opportunity" bits. Therefore, these three additional bits (for DS3 data) are obtained by using three of these "Stuff Opportunity" bits. As a consequence, three (3) of these nine (9) "Stuff Opportunity" bits, within each STS-1 SPE, will carry DS3 databits. The remaining six (6) "Stuff Opportunity" bits will typically function as "stuff" bits. In summary, for the "Ideal Case"; where there is no frequency offset between the DS3 and the STS-1 bit-rates, once this DS3 data-stream has been mapped into the STS-1 data-stream, then each and every STS-1 SPE will have the following "Stuff Opportunity" bit utilization. 3 "Stuff Opportunity" bits will carry DS3 data bits. 6 "Stuff Opportunity" bits will function as "stuff" bits In this case, this DS3 signal (which has now been mapped into STS-1) will be transported across the SONET network. As this STS-1 signal arrives at the "Destination PTE", this PTE will extract (or de-map) this DS3 datastream from each incoming STS-1 SPE. Now since each and every STS-1 SPE contains exactly 5592 DS3 data bits; then the bit rate of this DS3 signal will be exactly 44.736Mbps (such as it was when it was mapped into SONET, at the "Source" PTE).
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The 44.736Mbps + 1ppm Case
The "above example" was a very ideal case. In reality, there are going to be frequency offsets in both the DS3 and STS-1 signals. For instance Bellcore GR-499-CORE mandates that a DS3 signal have a bit rate of 44.736Mbps 20ppm. Hence, the bit-rate of a "Bellcore" compliant DS3 signal can vary from the exact correct frequency for DS3 by as much of 20ppm in either direction. Similarly, many SONET applications mandate that SONET equipment use at least a "Stratum 3" level clock as its timing source. This requirement mandates that an STS-1 signal must have a bit rate that is in the range of 51.84 4.6ppm. To make matters worse, there are also provisions for SONET equipment to use (what is referred to as) a "SONET Minimum Clock" (SMC) as its timing source. In this case, an STS-1 signal can have a bit-rate in the range of 51.84Mbps 20ppm. In order to convey the impact that frequency offsets (in either the DS3 or STS-1 signal) will impose on the bitstuffing behavior, and the resulting bit-rate, intrinsic jitter and wander within the DS3 signal that is being transported across the SONET network; let us assume that a DS3 signal, with a bit-rate of 44.736Mbps + 1ppm is being mapped into an STS-1 signal with a bit-rate of 51.84Mbps + 0ppm. In this case, the following things will occur.
* In general, most of the STS-1 SPE's will each transport 5592 DS3 data bits. * However, within a "one-second" period, a DS3 signal that has a bit-rate of 44.736Mbps + 1 ppm will deliver
approximately 44.7 additional bits (over and above that of a DS3 signal with a bit-rate of 44.736Mbps + 0 ppm). This means that this particular signal will need to "negative-stuff" or map in an additional DS3 data bit every (1/44.736 =) 22.35ms. In other words, this additional DS3 data bit will need to be mapped into about one in every (22.35ms * 8000 =) 178.8 STS-1 SPEs in order to avoid dropping any DS3 data-bits. What does this mean at the "Source" PTE? All of this means that as the "Source" PTE maps this DS3 signal, with a data rate of 44.736Mbps + 1ppm into an STS-1 signal, most of the resulting "outbound" STS-1 SPEs will transport 5592 DS3 data bits (e.g., 3 Stuff Opportunity bits will be carrying DS3 data bits, the remaining 6 Stuff Opportunity bits are "stuff" bits, as in the "Ideal" case). However, in approximately one out of 178.8 "outbound" STS-1 SPEs, there will be a need to insert an additional DS3 data bit within this STS-1 SPE. Whenever this occurs, then (for these particular STS1 SPEs) the SPE will be carrying 5593 DS3 data bits (e.g., 4 Stuff Opportunity bits will be carrying DS3 data bits, the remaining 5 Stuff Opportunity bits are "stuff" bits). Figure 39 presents an illustration of the STS-1 SPE traffic that will be generated by the "Source" PTE, during this condition. FIGURE 39. AN ILLUSTRATION OF THE STS-1 SPE TRAFFIC THAT WILL BE GENERATED BY THE "SOURCE" PTE, DS3 SIGNAL THAT HAS A BIT RATE OF 44.736MBPS + 1PPM, INTO AN STS-1 SIGNAL
WHEN MAPPING IN A
Extra DS3 Data Bit Stuffed Here
SPE # N 5592 5592 DS3 Data DS3 Data Bits Bits
SPE # N+1 5592 5592 DS3 Data DS3 Data Bits Bits
SPE # N+177 5592 5592 DS3 Data DS3 Data Bits Bits 5593 5593 DS3 Data DS3 Data Bits Bits
SPE # N+179 5592 5592 DS3 Data DS3 Data Bits Bits
Source Source PTE PTE
SPE # N+178
44.736Mbps + 1ppm
STS-1 SPE Data Stream
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What does this mean at the "Destination" PTE? In this case, this DS3 signal (which has now been mapped into an STS-1 data-stream) will be transported across the SONET network. As this STS-1 signal arrives at the "Destination" PTE, this PTE will extract (or demap) this DS3 data from each incoming STS-1 SPE. Now, in this case most (e.g., 177/178.8) of the incoming STS-1 SPEs will contain 5592 DS3 data-bits. Therefore, the nominal data rate of the DS3 signal being demapped from SONET will be 44.736Mbps. However, in approximately 1 out of every 178 incoming STS-1 SPEs, the SPE will carry 5593 DS3 data-bits. This means that (during these times) the data rate of the demapped DS3 signal will have an instantaneous frequency that is greater than 44.736Mbps. These "excursion" of the de-mapped DS3 data-rate, from the nominal DS3 frequency can be viewed as occurrences of "mapping/ de-mapping" jitter. Since each of these "bit-stuffing" events involve the insertion of one DS3 data bit, we can say that the amplitude of this "mapping/de-mapping" jitter is approximately 1UI-pp. From this point on, we will be referring to this type of jitter (e.g., that which is induced by the mapping and de-mapping process) as "demapping" jitter. Since this occurrence of "de-mapping" jitter is periodic and occurs once every 22.35ms, we can state that this jitter has a frequency of 44.7Hz. 9.2.2.3
The 44.736Mbps - 1ppm Case
In this case, let us assume that a DS3 signal, with a bit-rate of 44.736Mbps - 1ppm is being mapped into an STS-1 signal with a bit-rate of 51.84Mbps + 0ppm. In this case, the following this will occur.
* In general, most of the STS-1 SPEs will each transport 5592 DS3 data bits. * However, within a "one-second" period a DS3 signal that has a bit-rate of 44.736Mbps - 1ppm will deliver
approximately 45 too few bits below that of a DS3 signal with a bit-rate of 44.736Mbps + 0ppm. This means that this particular signal will need to "positive-stuff" or exclude a DS3 data bit from mapping every (1/44.736) = 22.35ms. In other words, we will need to avoid mapping this DS3 data-bit about one in every (22.35ms*8000) = 178.8 STS-1 SPEs. What does this mean at the "Source" PTE? All of this means that as the "Source" PTE maps this DS3 signal, with a data rate of 44.736Mbps - 1ppm into an STS-1 signal, most of the resulting "outbound" STS-1 SPEs will transport 5592 DS3 data bits (e.g., 3 Stuff Opportunity bits will be carrying DS3 data bits, the remaining 6 Stuff Opportunity bits are "stuff" bits). However, in approximately one out of 178.8 "outbound" STS-1 SPEs, there will be a need for a "positive-stuffing" event. Whenever these "positive-stuffing" events occur then (for these particular STS-1 SPEs) the SPE will carry only 5591 DS3 data bits (e.g., in this case, only 2 Stuff Opportunity bits will be carrying DS3 data-bits, and the remaining 7 Stuff Opportunity bits are "stuff" bits). Figure 40 presents an illustration of the STS-1 SPE traffic that will be generated by the "Source" PTE, during this condition.
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FIGURE 40. AN ILLUSTRATION OF THE STS-1 SPE TRAFFIC THAT WILL BE GENERATED BY THE SOURCE PTE, WHEN DS3 SIGNAL THAT HAS A BIT RATE OF 44.736MBPS - 1PPM, INTO AN STS-1 SIGNAL
DS3 Data Bit Excluded Here
SPE # N 5592 5592 DS3 Data DS3 Data Bits Bits
SPE # N+1 5592 5592 DS3 Data DS3 Data Bits Bits
SPE # N+177 5592 5592 DS3 Data DS3 Data Bits Bits 5591 5591 DS3 Data DS3 Data Bits Bits
SPE # N+179 5592 5592 DS3 Data DS3 Data Bits Bits
Source Source PTE PTE
SPE # N+178
44.736Mbps - 1ppm
STS-1 SPE Data Stream
What does this mean at the Destination PTE? In this case, this DS3 signal (which has now been mapped into an STS-1 data-stream) will be transported across the SONET network. As this STS-1 signal arrives at the "Destination" PTE, this PTE will extract (or demap) this DS3 data from each incoming STS-1 SPE. Now, in this case, most (e.g., 177/178.8) of the incoming STS-1 SPEs will contain 5592 DS3 data-bits. Therefore, the nominal data rate of the DS3 signal being demapped from SONET will be 44.736Mbps. However, in approximately 1 out of every 178 incoming STS-1 SPEs, the SPE will carry only 5591 DS3 data bits. This means that (during these times) the data rate of the demapped DS3 signal will have an instantaneous frequency that is less than 44.736Mbps. These "excursions" of the de-mapped DS3 data-rate, from the nominal DS3 frequency can be viewed as occurrences of mapping/demapping jitter with an amplitude of approximately 1UI-pp. Since this occurrence of "de-mapping" jitter is periodic and occurs once every 22.35ms, we can state that this jitter has a frequency of 44.7Hz. We talked about De-Mapping Jitter, What about De-Mapping Wander? The Telcordia and Bellcore specifications define "Wander" as "Jitter with a frequency of less than 10Hz". Based upon this definition, the DS3 signal (that is being transported by SONET) will cease to contain jitter and will now contain "Wander", whenever the frequency offset of the DS3 signal being mapped into SONET is less than 0.2ppm. 9.3
Jitter/Wander due to Pointer Adjustments
In the previous section, we described how a DS3 signal is asynchronously-mapped into SONET, and we also defined "Mapping/De-mapping" jitter. In this section, we will describe how occurrences within the SONET network will induce jitter/wander within the DS3 signal that is being transported across the SONET network. In order to accomplish this, we will discuss the following topics in detail.
* The concept of an STS-1 SPE pointer * The concept of Pointer Adjustments * The causes of Pointer Adjustments * How Pointer Adjustments induce jitter/wander within a DS3 signal being transported by that SONET network.
9.3.1 The Concept of an STS-1 SPE Pointer As mentioned earlier, the STS-1 SPE is not aligned to the STS-1 frame boundaries and is permitted to "float" within the Envelope Capacity. As a consequence, the STS-1 SPE will often times "straddle" across two
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consecutive STS-1 frames. consecutive STS-1 frames.
Figure 41 presents an illustration of an STS-1 SPE straddling across two
FIGURE 41. AN ILLUSTRATION OF AN STS-1 SPE STRADDLING ACROSS TWO CONSECUTIVE STS-1 FRAMES
TOH
STS-1 FRAME N
STS-1 FRAME N + 1
H1, H2 Bytes
J1 Byte (1st byte of SPE)
J1 Byte (1st byte of next SPE)
SPE can straddle across two STS-1 frames
A PTE that is receiving and terminating an STS-1 data-stream will perform the following tasks.
* It will acquire and maintain STS-1 frame synchronization with the incoming STS-1 data-stream. * Once the PTE has acquired STS-1 frame synchronization, then it will locate the J1 byte (e.g., the very byte
within the very next STS-1 SPE) within the Envelope Capacity by reading out the contents of the H1 and H2 bytes. The H1 and H2 bytes are referred to (in the SONET standards) as the SPE Pointer Bytes. When these two bytes are concatenated together in order to form a 16-bit word (with the H1 byte functioning as the "Most Significant Byte") then the contents of the "lower" 10 bit-fields (within this 16-bit word) reflects the location of the J1 byte within the Envelope Capacity of the incoming STS-1 data-stream. Figure 42 presents an illustration of the bit format of the H1 and H2 bytes, and indicates which bit-fields are used to reflect the location of the J1 byte.
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REFLECTING THE LOCATION OF THE
FIGURE 42. THE BIT-FORMAT OF THE 16-BIT WORD (CONSISTING OF THE H1 AND H2 BYTES) WITH THE 10 BITS, J1 BYTE, DESIGNATED
H1 Byte MSB
H2 Byte LSB
NNNNSSXXXXXXXXXX
10 Bit Pointer Expression
Figure 43 relates the contents within these 10 bits (within the H1 and H2 bytes) to the location of the J1 byte (e.g., the very first byte of the STS-1 SPE) within the Envelope Capacity. FIGURE 43. THE RELATIONSHIP BETWEEN THE CONTENTS OF THE "POINTER BITS" (E.G., THE 10-BIT EXPRESSION WITHIN THE H1 AND H2 BYTES) AND THE LOCATION OF THE J1 BYTE WITHIN THE ENVELOPE CAPACITY OF AN STS1 FRAME
TOH
The Pointer Value "0" is immediately After the H3 byte
A1 B1 D1 H1 B2 D4 D7 D10 S1
A2 E1 D2 H2 K1 D5 D8 D11 M0
C1/J0 F1 D3 H3 K2 D6 D9 D12 E2
522 609 696 0 87 174 261 348 435
523 610 697 1 88 175 262 349 436
******** ******** ** ***** ***** ******** ** ***** ***** ******** ** ******** ** ***** ***** ******** ** **
607 694 781 85 172 259 346 433 520
608 695 782 86 173 260 347 434 521
NOTES: 1. If the content of the "Pointer Bits" is "0x00" then the J1 byte is located immediately after the H3 byte, within the Envelope Capacity. 2. If the contents of the 10-bit expression exceed the value of 0x30F (or 782, in decimal format) then it does not contain a valid pointer value.
9.3.2
Pointer Adjustments within the SONET Network
The word SONET stands for "Synchronous Optical NETwork. This name implies that the entire SONET network is synchronized to a single clock source. However, because the SONET (and SDH) Networks can
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span thousands of miles, traverse many different pieces of equipments, and even cross International boundaries; in practice, the SONET/SDH network is NOT synchronized to a single clock source. In practice, the SONET/SDH network can be thought of as being divided into numerous "Synchronization Islands". Each of these "Synchronization Islands" will consist of numerous pieces of SONET Terminal Equipment. Each of these pieces of SONET Terminal Equipment will all be synchronized to a single Stratum-1 clock source which is the most accurate clock source within the Synchronization Island. Typically a "Synchronization Island" will consist of a single "Timing Master" equipment along with multiple "Timing Slave" pieces of equipment. This "Timing Master" equipment will be directly connected to the Stratum-1 clock source and will have the responsibility of distributing a very accurate clock signal (that has been derived from the Stratum 1 clock source) to each of the "Timing Slave" pieces of equipment within the "Synchronization Island". The purpose of this is to permit each of the "Timing Slave" pieces of equipment to be "synchronized" with the "Timing Master" equipment, as well as the Stratum 1 Clock source. Typically this "clock distribution" is performed in the form of a BITS (Building Integrated Timing Supply) clock, in which a very precise clock signal is provided to the other pieces of equipment via a T1 or E1 line signal. Many of these "Synchronization Islands" will use a Stratum-1" clock source that is derived from GPS pulses that are received from Satellites that operate at Geo-synchronous orbit. Other "Synchronization Islands" will use a Stratum-1" clock source that is derived from a very precise local atomic clock. As a consequence, different "Synchronization Islands" will use different Stratum 1 clock sources. The up-shot of having these "Synchronization Islands" that use different "Stratum-1 clock" sources, is that the Stratum 1 Clock frequencies, between these "Synchronization Islands" are likely to be slightly different from each other. These "frequencydifferences" within Stratum 1 clock sources will result in "clock-domain changes" as a SONET signal (that is traversing the SONET network) passes from one "Synchronization Island" to another. The following section will describe how these "frequency differences" will cause a phenomenon called "pointer adjustments" to occur in the SONET Network. 9.3.3 Causes of Pointer Adjustments The best way to discuss how pointer adjustment events occur is to consider an STS-1 signal, which is driven by a timing reference of frequency f1; and that this STS-1 signal is being routed to a network equipment (that resides within a different "Synchronization Island") and processes STS-1 data at a frequency of f2.
NOTE: Clearly, both frequencies f1 and f2 are at the STS-1 rate (e.g., 51.84MHz). However, these two frequencies are likely to be slightly different from each other.
Now, since the STS-1 signal (which is of frequency f1) is being routed to the network element (which is operating at frequency f2), the typical design approach for handling "clock-domain" differences is to route this STS-1 signal through a "Slip Buffer" as illustrated below.
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Clock Domain operating At frequency f1
STS-1 Data_IN STS-1 Clock_f1
STS-1 Data_OUT
SLIP BUFFER SLIP BUFFER
STS-1 Clock_f2
Clock Domain operating At Frequency f2.
In the "Slip Buffer, the "input" STS-1 data (labeled "STS-1 Data_IN") is latched into the FIFO, upon a given edge of the corresponding "STS-1 Clock_f1" input clock signal. The STS-1 Data (labeled "STS-1 Data_OUT") is clocked out of the Slip Buffer upon a given edge of the "STS-1 Clock_f2" input clock signal. The behavior of the data, passing through the "Slip Buffer" is now described for each possible relationship between frequencies f1 and f2.
If f1 = f2
If both frequencies, f1 and f2 are exactly equal, then the STS-1 data will be "clocked" into the "Slip Buffer" at exactly the same rate that it is "clocked out". In this case, the "Slip Buffer" will neither fill-up nor become depleted. As a consequence, no pointer-adjustments will occur in this STS-1 data stream. In other words, the STS-1 SPE will remain at a constant location (or offset) within each STS-1 envelope capacity for the duration that this STS-1 signal is supporting this particular service.
If f1 < f2
If frequency f1 is less than f2, then this means that the STS-1 data is being "clocked out" of the "Slip Buffer" at a faster rate than it is being clocked in. In this case, the "Slip Buffer" will eventually become depleted. Whenever this occurs, a typical strategy is to "stuff" (or insert) a "dummy byte" into the data stream. The purpose of stuffing this "dummy byte" is to compensate for the frequency differences between f1 and f2, and attempt to keep the "Slip Buffer, at a somewhat constant fill level.
NOTE: This "dummy byte" does not carry any valuable information (not for the user, nor for the system).
Since this "dummy byte" carries no useful information, it is important that the "Receiving PTE" be notified anytime this "dummy byte" stuffing occurs. This way, the Receiving Terminal can "know" not to treat this "dummy byte" as user data. Byte-Stuffing and Pointer Incrementing in a SONET Network Whenever this "byte-stuffing" occurs then the following other things occur within the STS-1 data stream.
During the STS-1 frame that contains the "Byte-Stuffing" event
a. The "stuff-byte" will be inserted into the byte position immediately after the H3 byte. This insertion of the "dummy byte" immediately after the H3 byte position will cause the J1 byte (and in-turn, the rest of the SPE) to be "byte-shifted" away from the H3 byte. As a consequence, the offset between the H3 byte position and the STS-1 SPE will now have been increased by 1 byte. b. The "Transmitting" Network Equipment will notify the remote terminal of this byte-stuffing event, by inverting certain bits within the "pointer word" (within the H1 and H2 bytes) that are referred to as "I" bits.
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Figure 45 presents an illustration of the bit-format within the 16-bit word (consist of the H1 and H2 bytes) with the "I" bits designated. FIGURE 45. AN ILLUSTRATION OF THE BIT FORMAT WITHIN THE 16-BIT WORD (CONSISTING OF THE H1 AND H2 BYTES) WITH THE "I" BITS DESIGNATED
H1 Byte MSB
H2 Byte LSB
NNNNSS ID ID ID ID ID
10 Bit Pointer Expression
NOTE: At this time the "I" bits are inverted in order to denote that an "incrementing" pointer adjustment event is currently occurring.
During the STS-1 frame that follows the "Byte-Stuffing" event
The "I" bits (within the "pointer-word") will be set back to their normal value; and the contents of the H1 and H2 bytes will be incremented by "1".
If f1 > f2
If frequency f1 is greater than f2, then this means that the STS-1 data is being clocked into the "Slip Buffer" at a faster rate than is being clocked out. In this case, the "Slip Buffer" will start to fill up. Whenever this occurs, a typical strategy is to delete (e.g., negative-stuff) a byte from the Slip Buffer. The purpose of this "negativestuffing" is to compensate for the frequency differences between f1 and f2; and to attempt to keep the "Slip Buffer" at a somewhat constant fill-level.
NOTE: This byte, which is being "un-stuffed" does carry valuable information for the user (e.g., this byte is typically a payload byte). Therefore, whenever this negative stuffing occurs, two things must happen.
a. The "negative-stuffed" byte must not be simply discarded. In other words, it must somehow also be transmitted to the remote PTE with the remainder of the SPE data. b. The remote PTE must be notified of the occurrence of these "negative-stuffing" events. Further, the remote PTE must know where to obtain this "negative-stuffed" byte. Negative-Stuffing and Pointer-Decrementing in a SONET Network Whenever this "byte negative-stuffing" occurs then the following other things occur within the STS-1 datastream.
During the STS-1 frame that contains the "Negative Byte-Stuffing" Event
a. The "Negative-Stuffed" byte will be inserted into the H3 byte position. Whenever an SPE data byte is inserted into the H3 byte position (which is ordinarily an unused byte), the number of bytes that will exist between the H3 byte and the J1 byte within the very next SPE will be reduced by 1 byte. As a consequence, in this case, the J1 byte (and in-turn, the rest of the SPE) will now be "byte-shifted" towards the H3 byte position. b. The "Transmitting" Network Element will notify the remote terminal of this "negative-stuff" event by inverting certain bits within the "pointer word" (within the H1 and H2 bytes) that are referred to as "D" bits.
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Figure 46 presents an illustration of the bit format within the 16-bit word (consisting of the H1 and H2 bytes) with the "D" bits designated. FIGURE 46. AN ILLUSTRATION OF THE BIT-FORMAT WITHIN THE 16-BIT WORD (CONSISTING OF THE H1 AND H2 "D" BITS DESIGNATED
BYTES) WITH THE
H1 Byte MSB
H2 Byte LSB
NNNNSS ID ID ID ID ID
10 Bit Pointer Expression
NOTE: At this time the "D" bits are inverted in order to denote that a "decrementing" pointer adjustment event is currently occurring.
During the STS-1 frame that follows the "Negative Byte-Stuffing" Event The "D" bits (within the pointer-word) will be set back to their normal value; and the contents of the H1 and H2 bytes will be decremented by one.
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9.3.4
The overall SONET network consists of numerous "Synchronization Islands". As a consequence, whenever a SONET signal is being transmitted from one "Synchronization Island" to another; that SONET signal will undergo a "clock domain" change as it traverses the network. This clock domain change will result in periodic pointer-adjustments occurring within this SONET signal. Depending upon the direction of this "clock-domain" shift that the SONET signal experiences, there will either be periodic "incrementing" pointer-adjustment events or periodic "decrementing" pointer-adjustment events within this SONET signal. Regardless of whether a given SONET signal is experiencing incrementing or decrementing pointer adjustment events, each pointer adjustment event will result in an abrupt 8-bit shift in the position of the SPE within the STS-1 data-stream. If this STS-1 signal is transporting an "asynchronously-mapped" DS3 signal; then this 8-bit shift in the location of the SPE (within the STS-1 signal) will result in approximately 8UIpp of jitter within the asynchronously-mapped DS3 signal, as it is de-mapped from SONET. In "Section 9.5, A Review of the Category I Intrinsic Jitter Requirements (per Telcordia GR-253-CORE) for DS3 applications" on page 110 we will discuss the "Category I Intrinsic Jitter Requirements (for DS3 Applications) per Telcordia GR-253CORE. However, for now we will simply state that this 8UIpp of intrinsic jitter far exceeds these "intrinsic jitter" requirements. In summary, pointer-adjustments events are a "fact of life" within the SONET/SDH network. Further, pointeradjustment events, within a SONET signal that is transporting an asynchronously-mapped DS3 signal, will impose a significant impact on the Intrinsic Jitter and Wander within that DS3 signal as it is de-mapped from SONET. 9.4
Clock Gapping Jitter
In most applications (in which the XRT75L03D will be used in a SONET De-Sync Application) the user will typically interface the XRT75L03D to a Mapper Device in the manner as presented below in Figure 47. FIGURE 47. ILLUSTRATION OF THE TYPICAL APPLICATIONS FOR THE XRT75L03D IN A SONET DE-SYNC APPLICATION
De-Mapped (Gapped) DS3 Data and Clock
TPDATA_n input pin
STS-N Signal
DS3 to STS-N DS3 to STS-N Mapper/ Mapper/ Demapper Demapper IC IC
XRT75L03D XRT75L03D
TCLK_n input
In this application, the Mapper IC will have the responsibility of receiving an STS-N signal (from the SONET Network) and performing all of the following operations on this STS-N signal.
* Byte-de-interleaving this incoming STS-N signal into N STS-1 signals * Terminating each of these STS-1 signals * Extracting (or de-mapping) the DS3 signal(s) from the SPEs within each of these terminated STS-1 signals.
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In this application, these Mapper devices can be thought of as multi-channel devices. For example, an STS-3 Mapper can be viewed as a 3-Channel DS3/STS-1 to STS-3 Mapper IC. Similarly, an STS-12 Mapper can be viewed as a 12-Channel DS3/STS-1 to STS-12 Mapper IC. Continuing on with this line of thought, if a Mapper IC is configured to receive an STS-N signal, and (from this STS-N signal) de-map and output N DS3 signals (towards the DS3 facility), then it will typically do so in the following manner.
* In many cases, the Mapper IC will output this DS3 signal, using both a "Data-Signal" and a "Clock-Signal". In
many cases, the Mapper IC will output the contents of an entire STS-1 data-stream via the Data-Signal.
* However, as the Mapper IC output this STS-1 data-stream, it will typically supply clock pulses (via the ClockSignal output) coincident to whenever a DS3 bit is being output via the Data-Signal. In this case, the Mapper IC will NOT supply a clock pulse coincident to when a TOH, POH, or any "non-DS3 data-bit" is being output via the "Data-Signal". Now, since the Mapper IC will output the entire STS-1 data stream (via the Data-Signal), the output ClockSignal will be of the form such that it has a period of 19.3ns (e.g., a 51.84MHz clock signal). However, the Mapper IC will still generate approximately 44,736,000 clock pulses during any given one second period. Hence, the clock signal that is output from the Mapper IC will be a horribly gapped 44.736MHz clock signal. One can view such a clock signal as being a very-jittery 44.736MHz clock signal. This jitter that exists within the "Clock-Signal" is referred to as "Clock-Gapping" Jitter. A more detailed discussion on how the user must handle this type of jitter is presented in "Section 9.8.2, Recommendations on Pre-Processing the Gapped Clocks (from the Mapper/ASIC Device) prior to routing this DS3 Clock and Data-Signals to the Transmit Inputs of the XRT75L03D" on page 121. 9.5
A Review of the Category I Intrinsic Jitter Requirements (per Telcordia GR-253-CORE) for DS3 applications
The "Category I Intrinsic Jitter Requirements" per Telcordia GR-253-CORE (for DS3 applications) mandates that the user perform a large series of tests against certain specified "Scenarios". These "Scenarios" and their corresponding requirements is summarized in Table 31, below. TABLE 31: SUMMARY OF "CATEGORY I INTRINSIC JITTER REQUIREMENT PER TELCORDIA GR-253-CORE, FOR DS3
APPLICATIONS
SCENARIO DESCRIPTION DS3 De-Mapping Jitter Single Pointer Adjustment
SCENARIO NUMBER
TELCORDIA GR-253-CORE CATEGORY I INTRINSIC JITTER REQUIREMENTS 0.4UI-pp
COMMENTS
Includes effects of De-Mapping and Clock Gapping Jitter
A1
0.3UI-pp + Ao
Includes effects of Jitter from Clock-Gapping, De-Mapping and Pointer Adjustments.NOTE: Ao is the amount of intrinsic jitter that was measured during the "DS3 DeMapping Jitter" phase of the Test. Includes effects of Jitter from Clock-Gapping, De-Mapping and Pointer Adjustments. Includes effects of Jitter from Clock-Gapping, De-Mapping and Pointer Adjustments. Includes effects of Jitter from Clock-Gapping, De-Mapping and Pointer Adjustments. Includes effects of Jitter from Clock-Gapping, De-Mapping and Pointer Adjustments. Includes effects of Jitter from Clock-Gapping, De-Mapping and Pointer Adjustments.
Pointer Bursts Phase Transients 87-3 Pattern 87-3 Add 87-3 Cancel
A2 A3 A4 A5 A5
1.3UI-pp 1.2UI-pp 1.0UI-pp 1.3UI-pp 1.3UI-pp
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TABLE 31: SUMMARY OF "CATEGORY I INTRINSIC JITTER REQUIREMENT PER TELCORDIA GR-253-CORE, FOR DS3
TELCORDIA GR-253-CORE CATEGORY I INTRINSIC JITTER REQUIREMENTS 1.0UI-pp 1.3UI-pp 1.3UI-pp
SCENARIO DESCRIPTION Continuous Pattern Continuous Add Continuous Cancel
SCENARIO NUMBER A4 A5 A5
COMMENTS
Includes effects of Jitter from Clock-Gapping, De-Mapping and Pointer Adjustments. Includes effects of Jitter from Clock-Gapping, De-Mapping and Pointer Adjustments. Includes effects of Jitter from Clock-Gapping, De-Mapping and Pointer Adjustments.
NOTE: All of these intrinsic jitter measurements are to be performed using a band-pass filter of 10Hz to 400kHz.
Each of the scenarios presented in Table 31, are briefly described below. 9.5.1 DS3 De-Mapping Jitter DS3 De-Mapping Jitter is the amount of Intrinsic Jitter that will be measured within the "Line" or "Facility-side" DS3 signal, (after it has been de-mapped from a SONET signal) without the occurrence of "Pointer Adjustments" within the SONET signal. Telcordia GR-253-CORE requires that the "DS3 De-Mapping" Jitter be less than 0.4UI-pp, when measured over all possible combinations of DS3 and STS-1 frequency offsets. 9.5.2 Single Pointer Adjustment Telcordia GR-253-CORE states that if each pointer adjustment (within a continuous stream of pointer adjustments) is separated from each other by a period of 30 seconds, or more; then they are sufficiently isolated to be considered "Single-Pointer Adjustments". Figure 48 presents an illustration of the "Single Pointer Adjustment" Scenario. FIGURE 48. ILLUSTRATION OF SINGLE POINTER ADJUSTMENT SCENARIO
Pointer Adjustment Events
>30s
Initialization
Cool Down
Measurement Period
Telcordia GR-253-CORE states that the Intrinsic Jitter that is measured (within the DS3 signal) that is ultimately de-mapped from a SONET signal that is experiencing "Single-Pointer Adjustment" events, must NOT exceed the value 0.3UI-pp + Ao.
NOTES: 1. Ao is the amount of Intrinsic Jitter that was measured during the "De-Mapping" Jitter portion of this test. 2. Testing must be performed for both Incrementing and Decrementing Pointer Adjustments.
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Figure 49 presents an illustration of the "Pointer Burst" Pointer Adjustment Scenario per Telcordia GR-253CORE. FIGURE 49. ILLUSTRATION OF BURST OF POINTER ADJUSTMENT SCENARIO
Pointer Adjustment Events
Pointer Adjustment Burst Train
t
0.5ms 0.5ms
>30s
Initialization
Cool Down
Measurement Period
Telcordia GR-253-CORE mandates that the Intrinsic Jitter, within the DS3 signal that is de-mapped from a SONET signal, which is experiencing the "Burst of Pointer Adjustment" scenario, must NOT exceed 1.3UI-pp. 9.5.4 Phase Transients Figure 50 presents an illustration of the "Phase Transients" Pointer Adjustment Scenario per Telcordia GR-253CORE. FIGURE 50. ILLUSTRATION OF "PHASE-TRANSIENT" POINTER ADJUSTMENT SCENARIO
Pointer Adjustment Events
Pointer Adjustment Burst Train
0.5s
0.25s
0.25s
t
>30s
Initialization
Cool Down
Measurement Period
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Telcordia GR-253-CORE mandates that the Intrinsic Jitter, within the DS3 signal that is de-mapped from a SONET signal, which is experiencing the "Phase Transient - Pointer Adjustment" scenario must NOT exceed 1.2UI-pp. 9.5.5 87-3 Pattern Figure 51 presents an illustration of the "87-3 Continuous Pattern" Pointer Adjustment Scenario per Telcordia GR-253-CORE. FIGURE 51. AN ILLUSTRATION OF THE 87-3 CONTINUOUS POINTER ADJUSTMENT PATTERN
Repeating 87-3 Pattern (see below)
Pointer Adjustment Events
Initialization
Measurement Period
87-3 Pattern
87 Pointer Adjustment Events
No Pointer Adjustments
T
NOTE: T ranges from 34ms to 10s (Req) T ranges from 7.5ms to 34ms (Obj)
Telcordia GR-253-CORE defines an "87-3 Continuous" Pointer Adjustment pattern, as a repeating sequence of 90 pointer adjustment events. Within this 90 pointer adjustment event, 87 pointer adjustments are actually executed. The remaining 3 pointer adjustments are never executed. The spacing between individual pointer adjustment events (within this scenario) can range from 7.5ms to 10seconds. Telcordia GR-253-CORE mandates that the Intrinsic Jitter, within the DS3 signal that is de-mapped from a SONET signal, which is experiencing the "87-3 Continuous" pattern of Pointer Adjustments, must not exceed 1.0UI-pp. 9.5.6 87-3 Add Figure 52 presents an illustration of the "87-3 Add Pattern" Pointer Adjustment Scenario per Telcordia GR-253CORE.
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T
t
Telcordia GR-253-CORE defines an "87-3 Add" Pointer Adjustment, as the "87-3 Continuous" Pointer Adjustment pattern, with an additional pointer adjustment inserted, as shown above in Figure 52. Telcordia GR-253-CORE mandates that the Intrinsic Jitter, within the DS3 signal that is de-mapped from a SONET signal, which is experiencing the "87-3 Add" pattern of Pointer Adjustments, must not exceed 1.3UI-pp. 9.5.7 87-3 Cancel Figure 53 presents an illustration of the 87-3 Cancel Pattern Pointer Adjustment Scenario per Telcordia GR253-CORE. FIGURE 53. ILLUSTRATION OF 87-3 CANCEL POINTER ADJUSTMENT SCENARIO
86 or 87 Pointer Adjustments
No Pointer Adjustments
T
Cancelled Pointer Adjustment
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Telcordia GR-253-CORE defines an "87-3 Cancel" Pointer Adjustment, as the "87-3 Continuous" Pointer Adjustment pattern, with an additional pointer adjustment cancelled (or not executed), as shown above in Figure 53. Telcordia GR-253-CORE mandates that the Intrinsic Jitter, within the DS3 signal that is de-mapped from a SONET signal, which is experiencing the "87-3 Cancel" pattern of Pointer Adjustments, must not exceed 1.3UIpp. 9.5.8 Continuous Pattern Figure 54 presents an illustration of the "Continuous" Pointer Adjustment Scenario per Telcordia GR-253CORE. FIGURE 54. ILLUSTRATION OF CONTINUOUS PERIODIC POINTER ADJUSTMENT SCENARIO
Repeating Continuous Pattern (see below)
Pointer Adjustment Events
Initialization
Measurement Period T
Telcordia GR-253-CORE mandates that the Intrinsic Jitter, within the DS3 signal that is de-mapped from a SONET signal, which is experiencing the "Continuous" pattern of Pointer Adjustments, must not exceed 1.0UIpp. The spacing between individual pointer adjustments (within this scenario) can range from 7.5ms to 10s. 9.5.9 Continuous Add Figure 55 presents an illustration of the "Continuous Add Pattern" Pointer Adjustment Scenario per Telcordia GR-253-CORE.
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Continuous Pointer Adjustments
Continuous Pointer Adjustments
T
t
Telcordia GR-253-CORE defines an "Continuous Add" Pointer Adjustment, as the "Continuous" Pointer Adjustment pattern, with an additional pointer adjustment inserted, as shown above in Figure 55. Telcordia GR-253-CORE mandates that the Intrinsic Jitter, within the DS3 signal that is de-mapped from a SONET signal, which is experiencing the "Continuous Add" pattern of Pointer Adjustments, must not exceed 1.3UI-pp. 9.5.10 Continuous Cancel Figure 56 presents an illustration of the "Continuous Cancel Pattern" Pointer Adjustment Scenario per Telcordia GR-253-CORE. FIGURE 56. ILLUSTRATION OF CONTINUOUS-CANCEL POINTER ADJUSTMENT SCENARIO
Continuous Pointer Adjustments
T
Cancelled Pointer Adjustment
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Telcordia GR-253-CORE defines a "Continuous Cancel" Pointer Adjustment, as the "Continuous" Pointer Adjustment pattern, with an additional pointer adjustment cancelled (or not executed), as shown above in Figure 56. Telcordia GR-253-CORE mandates that the Intrinsic Jitter, within the DS3 signal that is de-mapped from a SONET signal, which is experiencing the "Continuous Cancel" pattern of Pointer Adjustments, must not exceed 1.3UI-pp. 9.6 9.7
A Review of the DS3 Wander Requirements per ANSI T1.105.03b-1997. A Review of the Intrinsic Jitter and Wander Capabilities of the XRT75L03D in a typical system application
Intrinsic Jitter Test results
To be provided in the next revision of this data sheet.
The Intrinsic Jitter and Wander Test results are summarized in this section. 9.7.1 The Intrinsic Jitter Test results for the XRT75L03D in DS3 being de-mapped from SONET is summarized below in Table 2. TABLE 32: SUMMARY OF "CATEGORY I INTRINSIC JITTER TEST RESULTS" FOR SONET/DS3 APPLICATIONS
SCENARIO DESCRIPTION DS3 De-Mapping Jitter Single Pointer Adjustment Pointer Bursts Phase Transients 87-3 Pattern 87-3 Add 87-3 Cancel Continuous Pattern Continuous Add Continuous Cancel A1 SCENARIO NUMBER XRT75L03D INTRINSIC JITTER TEST RESULTS 0.13UI-pp TELCORDIA GR-253-CORE CATEGORY I INTRINSIC JITTER REQUIREMENTS 0.4UI-pp
0.201UI-pp
0.43UI-pp (e.g. 0.13UI-pp + 0.3UI-pp)
A2 A3 A4 A5 A5 A4
0.582UI-pp 0.526UI-pp 0.790UI-pp 0.926UI-pp 0.885UI-pp 0.497UI-pp
1.3UI-pp 1.2UI-pp 1.0UI-pp 1.3UI-pp 1.3UI-pp 1.0UI-pp
A5 A5
0.598UI-pp 0.589UI-pp
1.3UI-pp 1.3UI-pp
NOTES: 1. A detailed test report on our Test Procedures and Test Results is available and can be obtained by contacting your Exar Sales Representative. 2. These test results were obtained via the XRT75L03s mounted on our XRT94L43 12-Channel DS3/E3/STS-1 Mapper Evaluation Board. 3. These same results apply to SDH/AU-3 Mapping applications.
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Wander Measurement test results will be provided in the next revision of the XRT75L03D Data Sheet.
Designing with the XRT75L03D
In this section, we will discuss the following topics.
* How to design with and configure the XRT75L03D to permit a system to meet the above-mentioned Intrinsic
Jitter and Wander requirements.
* How is the XRT75L03D able to meet the above-mentioned requirements? * How does the XRT75L03D permits the user to comply with the SONET APS Recovery Time requirements of
50ms (per Telcordia GR-253-CORE)?
* How should one configure the XRT75L03D, if one needs to support "Daisy-Chain" Testing at the end
Customer's site? 9.8.1 How to design and configure the XRT75L03D to permit a system to meet the abovementioned Intrinsic Jitter and Wander requirements
As mentioned earlier, in most application (in which the XRT75L03D will be used in a SONET De-Sync Application) the user will typically interface the XRT75L03D to a Mapper device in the manner as presented below in Figure 57. In this application, the Mapper has the responsibility of receiving a SONET STS-N/OC-N signal and extracting as many as N DS3 signals from this signal. As a given channel within the Mapper IC extracts out a given DS3 signal (from SONET) it will typically be applying a Clock and Data signal to the "Transmit Input" of the LIU IC. Figure 57 presents a simple illustration as to how one channel, within the XRT75L03D should be connected to the Mapper IC. FIGURE 57. ILLUSTRATION OF THE XRT75L03D BEING CONNECTED TO A MAPPER IC FOR SONET DE-SYNC APPLICATIONS
De-Mapped (Gapped) DS3 Data and Clock
TPDATA_n input pin
STS-N Signal
DS3 to STS-N DS3 to STS-N Mapper/ Mapper/ Demapper Demapper IC IC
XRT75L03D XRT75L03D
TCLK_n input
As mentioned above, the Mapper IC will typically output a Clock and Data signal to the XRT75L03D. In many cases, the Mapper IC will output the contents of an entire STS-1 data-stream via the Data Signal to the XRT75L03D. However, the Mapper IC typically only supplies a clock pulse via the Clock Signal to the XRT75L03D coincident to whenever a DS3 bit is being output via the Data Signal. In this case, the Mapper IC would not supply a clock edge coincident to when a TOH, POH or any non-DS3 data-bit is being output via the Data-Signal.
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Figure 57 indicates that the Data Signal from the Mapper device should be connected to the TPDATA_n input pin of the LIU IC and that the Clock Signal from the Mapper device should be connected to the TCLK_n input pin of the LIU IC. In this application, the XRT75L03D has the following responsibilities.
* Using a particular clock edge within the "gapped" clock signal (from the Mapper IC) to sample and latch the
value of each DS3 data-bit that is output from the Mapper IC.
* To (through the user of the Jitter Attenuator block) attenuate the jitter within this "DS3 data" and "clock signal"
that is output from the Mapper IC.
* To convert this "smoothed" DS3 data and clock into industry-compliant DS3 pulses, and to output these
pulses onto the line. To configure the XRT75L03D to operate in the correct mode for this application, the user must execute the following configuration steps. a. Configure the XRT75L03D to operate in the DS3 Mode The user can configure a given channel (within the XRT75L03D) to operate in the DS3 Mode, by executing either of the following steps.
* If the XRT75L03D has been configured to operate in the Host Mode
The user can accomplish this by setting both Bits 2 (E3_n) and Bits 1 (STS-1/DS3*_n), within each of the "Channel Control Registers" to "0" as depicted below.
CHANNEL CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X06 CHANNEL 1 ADDRESS LOCATION = 0X0E CHANNEL 2 ADDRESS LOCATION = 0X16
BIT 7 Unused R/O 0 R/O 0 BIT 6 BIT 5 PRBS Enable Ch_n R/W 0 BIT 4 RLB_n R/W 0 BIT 3 LLB_n R/W 0 BIT 2 E3_n R/W 0 BIT 1 STS-1/DS3_n R/W 0 BIT 0 SR/DR_n R/W 0
* If the XRT75L03D has been configured to operate in the Hardware Mode
The user can accomplish this by pulling all of the following input pins "Low". Pin 76 - E3_0 Pin 94 - E3_1 Pin 85 - E3_2 Pin 72 - STS-1/DS3_0 Pin 98 - STS-1/DS3_1 Pin 81 - STS-1/DS3_2 b. Configure the XRT75L03D to operate in the Single-Rail Mode Since the Mapper IC will typically output a single "Data Line" and a "Clock Line" for each DS3 signal that it demaps from the incoming STS-N signal, it is imperative to configure each channel within the XRT75L03D to operate in the Single Rail Mode. The user can accomplish this by executing either of the following steps.
* If the XRT75L03D has been configured to operate in the Host Mode
The user can accomplish this by setting Bit 0 (SR/DR*), within the each of the "Channel Control" Registers to 1, as illustrated below.
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THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER CHANNEL CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X06 CHANNEL 1 ADDRESS LOCATION = 0X0E CHANNEL 2 ADDRESS LOCATION = 0X16
BIT 7 Unused BIT 6 BIT 5 PRBS Enable Ch_n R/O 0 R/W 0 BIT 4 RLB_n BIT 3 LLB_n BIT 2 E3_n BIT 1 STS-1/
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BIT 0 SR/DR_n
DS3_n
R/W 0 R/W 0 R/W 0 R/W 0 R/W 1
R/O 0
* If the XRT75L03D has been configured to operate in the Hardware Mode
Then the user should tie pin 65 (SR/DR*) to "High". c. Configure each of the three channels within the XRT75L03D to operate in the SONET De-Sync Mode The user can accomplish this by executing either of the following steps.
* If the XRT75L03D has been configured to operate in the Host Mode.
Then the user should set Bit D2 (JA0) to "0" and Bit D0 (JA1) to "1", within the Jitter Attenuator Control Register, as depicted below. JITTER ATTENUATOR CONTROL REGISTER - (CHANNEL 0 ADDRESS LOCATION = 0X07 CHANNEL 1 ADDRESS LOCATION = 0X0F CHANNEL 2 ADDRESS LOCATION = 0X17
BIT 7 BIT 6 Unused BIT 5 BIT 4 SONET APS Recovery Time DisableCh_n R/O 0 R/W 0 BIT 3 JA RESET Ch_n BIT 2 JA1 Ch_n BIT 1 JA in Tx Path Ch_n BIT 0 JA0 Ch_n
R/O 0
R/O 0
R/W 0
R/W 0
R/W 0
R/W 1
* If the XRT75L03D has been configured to operate in the Hardware Mode
Then the user should tie pin 44 (JA0) to a logic "HIGH" and pin 42 (JA1) to a logic "LOW". Once the user accomplishes either of these steps, then the Jitter Attenuator (within the XRT75L03D) will be configured to operate with a very narrow bandwidth. d. Configure the Jitter Attenuator (within each of three three channels) to operate in the Transmit Direction. The user can accomplish this by executing either the following steps.
* If the XRT75L03D has been configured to operate in the Host Mode.
Then the user should be Bit D1 (JATx/JARx*) to "1", within the Jitter Attenuator Control Register, as depicted below.
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JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07 CHANNEL 1 ADDRESS LOCATION = 0X0F CHANNEL 2 ADDRESS LOCATION = 0X17
BIT 7 BIT 6 Unused BIT 5 BIT 4 SONET APS Recovery Time DisableCh_n R/O 0 R/W 0 BIT 3 JA RESET Ch_n BIT 2 JA1 Ch_n BIT 1 JA in Tx Path Ch_n BIT 0 JA0 Ch_n
R/O 0
R/O 0
R/W 0
R/W 0
R/W 1
R/W 1
* If the XRT75L03D has been configured to operate in the Hardware Mode.
Then the user should tie pin 43 (JATx/JARx*) to "1". e. Enable the "SONET APS Recovery Time" Mode Finally, if the user intends to use the XRT75L03D in an Application that is required to reacquire proper SONET and DS3 traffic, prior within 50ms of an APS (Automatic Protection Switching) event (per Telcordia GR-253CORE), then the user should set Bit 4 (SONET APS Recovery Time Disable), within the "Jitter Attenuator Control" Register, to "0" as depicted below. JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07 CHANNEL 1 ADDRESS LOCATION = 0X0F CHANNEL 2 ADDRESS LOCATION = 0X17
BIT 7 BIT 6 Unused BIT 5 BIT 4 SONET APS Recovery Time DisableCh_n R/O 0 R/W 0 BIT 3 JA RESET Ch_n BIT 2 JA1 Ch_n BIT 1 JA in Tx Path Ch_n BIT 0 JA0 Ch_n
R/O 0
R/O 0
R/W 0
R/W 0
R/W 0
R/W 1
NOTES: 1. The ability to disable the "SONET APS Recovery Time" mode is only available if the XRT75L03D is operating in the Host Mode. If the XRT75L03D is operating in the "Hardware" Mode, then this "SONET APS Recovery Time Mode" feature will always be enabled. 2. The "SONET APS Recovery Time" mode will be discussed in greater detail in "Section 9.8.3, How does the XRT75L03D permit the user to comply with the SONET APS Recovery Time requirements of 50ms (per Telcordia GR-253-CORE)?" on page 126.
9.8.2
Recommendations on Pre-Processing the Gapped Clocks (from the Mapper/ASIC Device) prior to routing this DS3 Clock and Data-Signals to the Transmit Inputs of the XRT75L03D
In order to minimize the effects of "Clock-Gapping" Jitter within the DS3 signal that is ultimately transmitted to the DS3 Line (or facility), we recommend that some "pre-processing" of the "Data-Signals" and "Clock-Signals" (which are output from the Mapper device) be implemented prior to routing these signals to the "Transmit Inputs" of the XRT75L03D.
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SOME NOTES PRIOR TO STARTING THIS DISCUSSION:
Our simulation results indicate that Jitter Attenuator PLL (within the XRT75L03D LIU IC) will have no problem handling and processing the "Data-Signal" and "Clock-Signal" from a Mapper IC/ASIC if no pre-processing has been performed on these signals. In order words, our simulation results indicate that the Jitter Attenuator PLL (within the LIU IC) will have no problem handling the "worst-case" of 59 consecutive bits of no clock pulses in the "Clock-Signal (due to the Mapper IC processing the TOH bytes, an Incrementing Pointer-Adjustmentinduced "stuffed-byte", the POH byte, and the two fixed-stuff bytes within the STS-1 SPE, etc), immediately followed be processing clusters of DS3 data-bits (as shown in Figure 37) and still comply with the "Category I Intrinsic Jitter Requirements per Telcordia GR-253-CORE for DS3 applications.
NOTE: If this sort of "pre-processing" is already supported by the Mapper device that you are using, then no further action is required by the user.
9.8.2.2
OUR PRE-PROCESSING RECOMMENDATIONS
For the time-being, we recommend that the customer implement the "pre-processing" of the DS3 "Data-Signal" and "Clock-Signal" as described below. Currently we are aware that some of the Mapper products on the Market do implement this exact "pre-processing" algorithm. However, if the customer is implementing their Mapper Design in an ASIC or FPGA solution, then we strongly recommend that the user implement the necessary logic design to realize the following recommendations. Some time ago, we spent some time, studying (and then later testing our solution with) the PM5342 OC-3 to DS3 Mapper IC from PMC-Sierra. In particular, we wanted to understand the type of "DS3 Clock" and "Data" signal that this DS3 to OC-3 Mapper IC outputs. During this effort, we learned the following. 1. This "DS3 Clock" and "Data" signal, which is output from the Mapper IC consists of two major "repeating" patterns (which we will refer to as "MAJOR PATTERN A" and "MAJOR PATTERN B". The behavior of each of these patterns is presented below.
MAJOR PATTERN A MAJOR PATTERN A consists of two "sub" or minor-patterns, (which we will refer to as "MINOR PATTERN P1 and P2). MINOR PATTERN P1 consists of a string of seven (7) clock pulses, followed by a single gap (no clock pulse). An illustration of MINOR PATTERN P1 is presented below in Figure 58. FIGURE 58. ILLUSTRATION OF MINOR PATTERN P1
Missing Clock Pulse
1
2
3
4
5
6
7
It should be noted that each of these clock pulses has a period of approximately 19.3ns (or has an "instantaneously frequency of 51.84MHz). MINOR Pattern P2 consists of string of five (5) clock pulses, which is also followed by a single gap (no clock pulse). An illustration of Pattern P2 is presented below in Figure 59.
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FIGURE 59. ILLUSTRATION OF MINOR PATTERN P2
Missing Clock Pulse
1
2
3
4
5
HOW MAJOR PATTERN A IS SYNTHESIZED MAJOR PATTERN A is created (by the Mapper IC) by:
* Repeating MINOR PATTERN P1 (e.g., 7 clock pulses, followed by a gap) 63 times. * Upon completion of the 63rd transmission of MINOR PATTERN P1, MINOR PATTERN P2 is transmitted
repeatedly 36 times. Figure 60 presents an illustration which depicts the procedure that is used to synthesize MAJOR PATTERN A FIGURE 60. ILLUSTRATION OF PROCEDURE WHICH IS USED TO SYNTHESIZE MAJOR PATTERN A
Repeats 63 Times MINOR PATTERN P1
Repeats 36 Times MINOR PATTERN P2
Hence, MAJOR PATTERN A consists of "(63 x 7) + (36 x 5)" = 621 clock pulses. These 621 clock pulses were delivered over a period of "(63 x 8) + (36 x 6)" = 720 STS-1 (or 51.84MHz) clock periods. MAJOR PATTERN B MAJOR PATTERN B consists of three sub or minor-patterns (which we will refer to as "MINOR PATTERNS P1, P2 and P3). MINOR PATTERN P1, which is used to partially synthesize MAJOR PATTERN B, is exactly the same "MINOR PATTERN P1" as was presented above in Figure 30. Similarly, the MINOR PATTERN P2, which is also used to partially synthesize MAJOR PATTERN B, is exactly the same "MINOR PATTERN P2" as was presented in Figure 31. MINOR PATTERN P3 (which has yet to be defined) consists of a string of six (6) clock pulses, which contains no gaps. An illustration of MINOR PATTERN P3 is presented below in Figure 61.
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THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER FIGURE 61. ILLUSTRATION OF MINOR PATTERN P3
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1
2
3
4
5
6
HOW MAJOR PATTERN B IS SYNTHESIZED MAJOR PATTERN B is created (by the Mapper IC) by:
* Repeating MINOR PATTERN P1 (e.g., 7 clock pulses, followed by a gap) 63 times. * Upon completion of the 63rd transmission of MINOR PATTERN P1, MINOR PATTERN P2 is transmitted
repeatedly 36 times.
* pon completion of the 35th transmission of MINOR PATTERN P2, MINOR PATTERN P3 is transmitted once.
Figure 62 presents an illustration which depicts the procedure that is used to synthesize MAJOR PATTERN B. FIGURE 62. ILLUSTRATION OF PROCEDURE WHICH IS USED TO SYNTHESIZE PATTERN B
Transmitted 1 Time Repeats 63 Times PATTERN P1 Repeats 35 Times PATTERN P2 PATTERN P3
Hence, MAJOR PATTERN B consists of "(63 x 7) + (35 x 5)" + 6 = 622 clock pulses. These 622 clock pulses were delivered over a period of "(63 x 8) + (35 x 6) + 6 = 720 STS-1 (or 51.84MHz) clock periods. PUTTING THE PATTERNS TOGETHER Finally, the DS3 to OC-N Mapper IC clock output is reproduced by doing the following.
* MAJOR PATTERN A is transmitted two times (repeatedly). * After the second transmission of MAJOR PATTERN A, MAJOR PATTERN B is transmitted once. * Then the whole process repeats.
Throughout the remainder of this document, we will refer to this particular pattern as the "SUPER PATTERN". Figure 63 presents an illustration of this "SUPER PATTERN" which is output via the Mapper IC.
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FIGURE 63. ILLUSTRATION OF THE SUPER PATTERN WHICH IS OUTPUT VIA THE "OC-N TO DS3" MAPPER IC
PATTERN A
PATTERN A
PATTERN B
CROSS-CHECKING OUR DATA
* Each SUPER PATTERN consists of (621 + 621 + 622) = 1864 clock pulses. * The total amount of time, which is required for the "DS3 to OC-N Mapper" IC to transmit this SUPER
PATTERN is (720 + 720 + 720) = 2160 "STS-1" clock periods.
* This amount to a period of (2160/51.84MHz) = 41,667ns. * In a period of 41, 667ns, the XRT75L03D (when configured to operate in the DS3 Mode), will output a total
(41,667ns x 44,736,000) = 1864 uniformly spaced DS3 clock pulses.
* Hence, the number of clock pulses match.
APPLYING THE SUPER PATTERN TO THE XRT75L03D Whenever the XRT75L03D is configured to operate in a "SONET De-Sync" application, the device will accept a continuous string of the above-defined SUPER PATTERN, via the TCLK input pin (along with the corresponding data). The channel within the XRT75L03D (which will be configured to operate in the "DS3" Mode) will output a DS3 line signal (to the DS3 facility) that complies with the "Category I Intrinsic Jitter Requirements - per Telcordia GR-253-CORE (for DS3 applications). This scheme is illustrated below in Figure 64. FIGURE 64. SIMPLE ILLUSTRATION OF THE XRT75L03D BEING USED IN A SONET DE-SYNCHRONIZER" APPLICATION
De-Mapped (Gapped) DS3 Data and Clock
TPDATA_n input pin
STS-N Signal
DS3 to STS-N DS3 to STS-N Mapper/ Mapper/ Demapper Demapper IC IC
XRT75L03D XRT75L03D
TCLK_n input
According to this figure, the Jitter Attenuator will receive a very jitter DS3 or E3 signal (e.g., data and clock signals) from the Mapper device via the "Transmit System-side" input pins of the LIU IC.
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How does the XRT75L03D permit the user to comply with the SONET APS Recovery Time requirements of 50ms (per Telcordia GR-253-CORE)?
Telcordia GR-253-CORE, Section 5.3.3.3 mandates that the "APS Completion" (or Recovery) time be 50ms or less. Many of our customers interpret this particular requirement as follows. "From the instant that an APS is initiated on a high-speed SONET signal, all lower-speed SONET traffic (which is being transported via this "high-speed" SONET signal) must be fully restored within 50ms. Similarly, if the "high-speed" SONET signal is transporting some PDH signals (such as DS1 or DS3, etc.), then those entities that are responsible for acquiring and maintaining DS1 or DS3 frame synchronization (with these DS1 or DS3 data-streams that have been de-mapped from SONET) must have re-acquired DS1 or DS3 frame synchronization within 50ms" after APS has been initiated." The XRT75L03D was designed such that the DS3 signals that it receives from a SONET Mapper device and processes will comply with the Category I Intrinsic Jitter requirements per Telcordia GR-253-CORE. Reference 1 documents some APS Recovery Time testing, which was performed to verify that the Jitter Attenuator blocks (within the XRT75L03D) device that permit it to comply with the Category I Intrinsic Jitter Requirements (for DS3 Applications) per Telcordia GR-253-CORE, do not cause it to fail to comply with the "APS Completion Time" requirements per Section 5.3.3.3 of Telcordia GR-253-CORE. However, Table 3 presents a summary of some APS Recovery Time requirements that were documented within this test report. Table 3, TABLE 33: MEASURED APS RECOVERY TIME AS A FUNCTION OF DS3 PPM OFFSET
DS3 PPM OFFSET (PER W&G ANT-20SE) -99 ppm -40ppm -30 ppm -20 ppm -10 ppm 0 ppm +10 ppm +20 ppm +30 ppm +40 ppm +99 ppm MEASURED APS RECOVERY TIME (PER LOGIC ANALYZER) 1.25ms 1.54ms 1.34ms 1.49ms 1.30ms 1.89ms 1.21ms 1.64ms 1.32ms 1.25ms 1.35ms
NOTE: The APS Completion (or Recovery) time requirement is 50ms.
Configuring the XRT75L03D to be able to comply with the SONET APS Recovery Time Requirements of 50ms Quite simply, the user can configure a given Jitter Attenuator block (associated with a given channel) to (1) comply with the "APS Completion Time" requirements per Telcordia GR-253-CORE, and (2) also comply with the "Category I Intrinsic Jitter Requirements per Telcordia GR-253-CORE (for DS3 applications) by making sure that Bit 4 (SONET APS Recovery Time Disable Ch_n), within the Jitter Attenuator Control Register is set to "0" as depicted below.
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JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07 CHANNEL 1 ADDRESS LOCATION = 0X0F CHANNEL 2 ADDRESS LOCATION = 0X17
BIT 7 BIT 6 Unused BIT 5 BIT 4 SONET APS Recovery Time Disable Ch_n R/O 0 R/W 0 BIT 3 JA RESET Ch_n BIT 2 JA1 Ch_n BIT 1 JA in Tx Path Ch_n BIT 0 JA0 Ch_n
R/O 0
R/O 0
R/W 0
R/W 0
R/W 1
R/W 1
NOTE: The user can only disable the "SONET APS Recovery Time Mode" if the XRT75L03D is operating in the Host Mode. If the user is operating the XRT75L03D in the Hardware Mode, then the user will have NO ability to disable the "SONET APS Recovery Time Mode" feature.
9.8.4
How should one configure the XRT75L03D, if one needs to support "Daisy-Chain" Testing at the end Customer's site?
Daisy-Chain testing is emerging as a new requirements that many of our customers are imposing on our SONET Mapper and LIU products. Many System Designer/Manufacturers are finding out that whenever their end-customers that are evaluating and testing out their systems (in order to determine if they wish to move forward and start purchasing this equipment in volume) are routinely demanding that they be able to test out these systems with a single piece of test equipment. This means that the end-customer would like to take a single piece of DS3 or STS-1 test equipment and (with this test equipment) snake the DS3 or STS-1 traffic (that this test equipment will generate) through many or (preferably all) channels within the system. For example, we have had request from our customers that (on a system that supports OC-192) our silicon be able to support this DS3 or STS-1 traffic snaking through the 192 DS3 or STS-1 ports within this system. After extensive testing, we have determined that the best approach to complying with test "Daisy-Chain" Testing requirements, is to configure the Jitter Attenuator blocks (within each of the Channels within the XRT75L03D) into the "32-Bit" Mode. The user can configure the Jitter Attenuator block (within a given channel of the XRT75L03D) to operate in this mode by settings in the table below. JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07 CHANNEL 1 ADDRESS LOCATION = 0X0F CHANNEL 2 ADDRESS LOCATION = 0X17
BIT 7 BIT 6 Unused BIT 5 BIT 4 SONET APS Recovery Time Disable Ch_n R/O 0 R/W 0 BIT 3 JA RESET Ch_n BIT 2 JA1 Ch_n BIT 1 JA in Tx Path Ch_n BIT 0 JA0 Ch_n
R/O 0
R/O 0
R/W 0
R/W 1
R/W 1
R/W 0
REFERENCES 1. TEST REPORT - AUTOMATIC PROTECTION SWITCHING (APS) RECOVERY TIME TESTING WITH THE XRT94L43 DS3/E3/STS-1 TO STS-12 MAPPER IC - Revision C Silicon
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ORDERING INFORMATION
PART NUMBER XRT75L03DIV PACKAGE 14 x 20 mm 128 Pin LQFP OPERATING TEMPERATURE RANGE - 40C to + 85C
PACKAGE DIMENSIONS - 14X20 MM, 128 PIN PACKAGE
D D1
102
65
103
64
C o p p e r H e a t s lu g s o ld e r p la te d e x p o s e d o n p a c k a g e b o tto m
E1
128
39
A2
1
e B
38
A C A1
N o te : T h e c o n tr o l d im e n s io n s a re th e m illim e te r c o lu m n T h e H e a t S lu g is a t th e c e n te r o f th e p a c k a g e .
IN C H E S SYMBOL A A1 A2 B C D D1 E E1 e L

L
M IL L IM E T E R S MAX M IN 1 .4 0 0 .0 5 1 .3 5 0 .1 7 0 .0 9 2 1 .8 0 1 9 .9 0 1 5 .8 0 1 3 .9 0 MAX 1 .6 0 0 .1 5 1 .4 5 0 .2 7 0 .2 0 2 2 .2 0 2 0 .1 0 1 6 .2 0 1 4 .1 0
M IN 0 .0 5 5 0 .0 0 2 0 .0 5 3 0 .0 0 7 0 .0 0 4 0 .8 5 8 0 .7 8 3 0 .6 2 2 0 .5 4 7
0 .0 6 3 0 .0 0 6 0 .0 5 7 0 .0 1 1 0 .0 0 8 0 .8 7 4 0 .7 9 1 0 .6 3 8 0 .5 5 5
0 .0 2 0 B S C 0 .0 1 8 0o 0 .3 7 0 0 .0 3 0 7o 0 .3 9 0 0 .4 5 0o 9 .4 0
0 .5 0 B S C 0 .7 5 7o 9 .9 0
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REVISION 1.0.0 DATE June 2003 Initial issue COMMENTS
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NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2003 EXAR Corporation Datasheet June 2003. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
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